Base of Q2 needs a resistor to ground to bleed off the emitter to base current that will accumulate on C2. Time constant of that resistor and C2 must be faster than the highest switching speed so Q2 can be fully off before the next high pulse arrives.
I made the same mistake with my circuit, except the accumulated charge will be a lot smaller with only parasitic capacitance.
The only thing I tried to do was arrive at: When the uc voltage output is low, the current through the next transistor is zero. If I understood the request correctly, I think it will work, as in, "fail in the off condition".
I can not interpret what Scott Wang said a a sentence, so I did not try to explain how, "the input is feedback".
Bedtime now. Sorry guys. The last time I woke up was Saturday at 2 pm. (Probably why I thought this was still Saturday )
I made the same mistake with my circuit, except the accumulated charge will be a lot smaller with only parasitic capacitance.
The only thing I tried to do was arrive at: When the uc voltage output is low, the current through the next transistor is zero. If I understood the request correctly, I think it will work, as in, "fail in the off condition".
I can not interpret what Scott Wang said a a sentence, so I did not try to explain how, "the input is feedback".
Bedtime now. Sorry guys. The last time I woke up was Saturday at 2 pm. (Probably why I thought this was still Saturday )
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