You have to measure frequency and duty cycle first, so the gate (resolution of measurement) controls the latency to update.

So the new output can be generated within one cycle of the input?

 

Here is a block diagram which could be implemented in a microcontroller, CPLD or discrete logic parts. Use an up counter to measure the width of four of the incoming PWM pulses. At the end of the fourth period, transfer the count to a down counter and immediately start an output cycle at 1/4 of the input frequency which is active until the down counter reaches 0. Rinse and repeat. I didn't show all the control signals. Just enough to illustrate the concept. All digital. Very accurate. The synchronizer is the usual dual flip-flop input. Think of it as added together the width of four of the input pulses and output them as a single pulse at 1/4 the frequency.

The microcontroller version uses an input capture function with a output compare function (PWM). The CPLD and discrete logic versions are basically the same. Four of the input cycles are added which is the way to do it for best accuracy.

 

Here is a solution. Right now error seems to be ~ 1/2% which I think is
too high. Will look at this some more tomorrow. Single chip solution.
Code ~ 20 lines.

This will accommodate a wide range of input Frequencies.



The test PWMtestFreq and LCD can be eliminated in final design.


Regards, Dana.

 

So the new output can be generated within one cycle of the input?

Short answer, No.

Latency is the gate time for the freq cntr, so if gate time is 100 mS corresponding
to a resolution in measurement of 10 Hz the latency is ~ 100 mS.

However in this design, at 4 Khz in, because I am counting 1 uS pulses, the
latency is closer to 1/2 mS. This is because I am using cntrs as reciprocal counters,
and the input signal is the gate. Also that includes ISR response time and the
fact I am using floating point math for calculation of duty cycle. That of course
can be converted to integer math which would help. I got lazy.

As you raise the clock to the cntrs you can lower the latency even further. But
you trade off power, cntr size, and in this type of embedded micro you are limited
in clocking rate of cntrs. ~ 30 Mhz for full featured cntrs, 80 Mhz bare bones....


Regards, Dana.

 

Additional work resulted in ~.2% (point 2%) duty cycle error at 8 Khz
source. Drops to ~ zero (limitations of PWM and CNTR depth and scope
accuracy) at 4 Khz


Regards, Dana.

 

~.2% (point 2%)

Should be written as 0.2%