sequential circuits, MMExer5.6

Thread Starter

PG1995

Joined Apr 15, 2011
818
Hi

Please have a look on the attachment and help me with the query there and please see if I'm doing it correctly. The manual once again has its own way!

As you can see, the question statement requires me to either use NAND or AND gates for connections with decoder's outputs. I understand that two-level NAND implementation is equivalent to AND-OR implementation and I will get normal uncomplemented output for a function. But if I use AND gate instead, then I have to use minterms for which function is zero because NAND-AND implementation is used to implement the complement of a function. (I have assumed that the decoder is made with NAND gates).

Thank you. By the way, there is some problem with the editor I wasn't able to attach more than one file. When I try to attach another one, the previous one gets replaced. This also happened some days ago.

Regards
PG
 

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Georacer

Joined Nov 25, 2009
5,182
I think you should stop using the manual by now, it only adds to your confusion.

It's not apparent to me that the decoder, built with NAND gates would have active LOW ouptputs. But let's take it as a given.

You thought correctly about F1 and F2, and F3 too, implementing the inverted function. An AND gate for F3', instead of a NAND would to the job.

Think about it: If F3' is FALSE, the decoder outputs only HIGH and the AND gate gives HIGH.
If F3' is TRUE, the decoder outputs one LOW and the AND gate gives a LOW too.
 

Thread Starter

PG1995

Joined Apr 15, 2011
818
Thank you very much.

It's not apparent to me that the decoder, built with NAND gates would have active LOW ouptputs. But let's take it as a given.
1: I don't get your point here. A decoder built with AND gates would have active HIGH outputs, right? For example, for this minterm, ABC'D', an AND gate would have HIGH output when this minterm is present on its inputs. But if we had used a NAND gate, then the presence of this minterm would only be confirmed by LOW output of NAND gate because for all other combinations output of NAND gate would be HIGH. Do I make any sense? Please let me know. Thanks.

2: I think you have missed my one query embedded in the attachment in my last post. In the question statement we have F3 (A,B,C)=Ʃ(2,3,5,6,7) and the question statement also requires me to minimize the number of inputs in the external gates. F3 would be false for these minterms (0,1,4). So I implemented F3' instead of F3 but used an inverter after NAND gate. Is it correct? By the way, this is how someone has done it. Isn't it wrong? You see, he has implemented POS (at least it looks like this) using NAND-NOR logic. Please comment. Thanks a lot.

Best regards
PG
 

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Georacer

Joined Nov 25, 2009
5,182
About your first question: Take a look at this datasheet (http://www.fairchildsemi.com/ds/MM/MM74HCT138.pdf) of a 3-to-8 active LOW decoder. Look at page 2 on the logic diagram. Would you say that it is build solely by NAND gates? I 'd say no.

On your second question, I guess I said things more complicated than I should. I just commented that instead of having a NAND gate and a NOT gate for F3, you should merge them into an AND gate.

About that someone else's circuit, first of all, if the decoder has active LOW outputs it should be noted by placing circles on the outputs. Supposing that the decoder has in fact active LOW outputs, he has implemented F3' in the last function. That is because a decoder energizes the minterms of its input, not the maxterms.
For example: for ABC=000, all decoder outputs are HIGH and the result is LOW - correct.
For ABC=001, minterm 1 is LOW, but overall the AND gate results to LOW - wrong.
For the circuit of F3 to display HIGH on a correct combination, all three minterms must be active. In general that isn't true.

So, in short, his solution is wrong.
 
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