Hi all,
I have been reading the AN attached, and if I understand correctly, SCR latchup in CMOS ICs is only a risk when a P-channel and an N-channel find themselves in close proximity to each other.
Is this a common scenario in most all CMOS ICs or just when you have a push pull output stage?
Regards,
I have been reading the AN attached, and if I understand correctly, SCR latchup in CMOS ICs is only a risk when a P-channel and an N-channel find themselves in close proximity to each other.
Is this a common scenario in most all CMOS ICs or just when you have a push pull output stage?
Regards,
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