Schmitt trigger's hysteresis voltage relation with power and freq.

Thread Starter

Alex_Khan

Joined May 27, 2020
59
Hello.
I would like a better understanding regarding Schmitt-trigger. What I know is: the wider the hysteresis width is, the more it provides noise immunity.

But I am curious about the relationship between incoming signal frequency and the hysteresis width?
And also the relationship of power and hysteresis width?

Thanks.
 

Papabravo

Joined Feb 24, 2006
18,422
There are a variety of methods used to determine the threshold trip points of a Schmitt-Trigger device. Your question is a bit vague, but:
AFAIK there is no relationship between incoming signal frequency and hysteresis width (N.B. the difference between the trip points).
Power consumption also has no connection to hysteresis width that I am aware of but depending on the IC technology may depend on the supply voltage and the switching frequency. It would help if you could be more specific, and maybe provide an annotated schematic of a circuit you may be considering.
 

Ian0

Joined Aug 7, 2020
5,131
If you’re thinking of a CMOS Schmitt trigger (4093, 74hc14, 74hc132) then power consumption is the same as any other logic gate. Extremely little if the input is at Vdd or Vss, and rather more than you would expect -almost 1mA - if the inputs are hovering about somewhere in between.
The Schmitt trigger nicely tidies up its output signals, but an input halfway between Vss and Vdd makes it consume power.
A 74HC14 with just one gate wired as a relaxation oscillator can consume more power than a CMOS 555.

Hysteresis levels only vary with supply voltage, not frequency.
interestingly, they seem to be more tightly defined in the 74LVC series than in 74HC.
 

Thread Starter

Alex_Khan

Joined May 27, 2020
59
Thanks, @Ian0 @Papabravo and @ericgibbs for your response.
To be more specific, I have added schematic and related results.
I am retrieving the 1Mhz original message signal from the receiving signal, for that I used ST. In order to have a minimum signal delay, I am limited to a very narrow hysteresis width [show] based on the receiving signal. -Widening hysteresis leads to high signal delay, which is not appreciable. Furthermore, due to narrow hysteresis, the design is vulnerable to noise.
-How can I overcome these limitations and what will be the relation of hysteresis with power consumption and frequency (if freq changes from 1Mhz)

Thanks.
 

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ericgibbs

Joined Jan 29, 2010
15,524
hi Alex,
Looking on the right side image of the 'square' wave, how is the data encoded on the 1MHz pulse train.
It appears to be from +3.5V to +5V.
Is it the amplitude of this 'part' of the signal or the absence or presence of the 1MHz pulse.

Basically, how is the data encoded on the 1MHz signal.?

E
Is how the 'Sine' wave is before the comparator.?
Capture.JPG
 
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Papabravo

Joined Feb 24, 2006
18,422
I believe it is a mistake to think that hysteresis has anything to do with signal delay. The propagation delay in a device is pretty much fixed and quantifiable. Once the trip points are set, they are pretty much fixed as well. That is, they occur at the same points on each and every repetition of the waveform. I'm not at all sure what you are going on about.
 

Papabravo

Joined Feb 24, 2006
18,422
The following simulation, using a common comparator model may be helpful in examining the way the upper and lower threshold points can be calculated and controlled. As you can see, the hysteresis does not depend on the things you think it does.

1645722262664.png
 
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