Hi...

Our teacher asked us to simulate the right side of a circuit that is a NAND port. That right side of the circuit is attached.
I'm trying to prove with LTSpice that the attached circuit (which is part of a circuit that is supposed to work like a NAND port), knowing that Logic Level 0 is Vce between 0V and 1V and Logic Level 1 is Vce between 4V and 5V, needs to have such a Vbb that makes the transistor work within those limits for Level 0 and Level 1.

So, using the net equations for output and input, I have calculated Ic, then Ib and lastly Vbb for Logic Level 0 and Logic Level 1.

For Logic Level 1 I found Ic=455μA, Ib=2.27μA and Vbb=0.927V
For Logic Level 0 I found Ic=1.83mA, Ib=9.8μA and Vbb=1.61V

But if I try these values for Vbb in LTSpice, the Vbb=0.927V looks like OK because Vce < 1V which is OK for Logic Level 0, but for Vbb=1.61V I should get Vce>4V but LTSpice is outputing a value under 3.8V.

Is there anything wrong with my calcs or can it be due to Vbe of LTSpice to be lower than 0.7V???

 

The circuit just a inverter not a nand gate, and Rb is too big.
If you want to be a nand gate then you can add two diodes and on resistor or add two bjts to combine a and gate.

 

The circuit just a inverter not a nand gate, and Rb is too big.
If you want to be a nand gate then you can add two diodes and on resistor or add two bjts to combine a and gate.

I think it's another case of a contrived example intended to make a simple circuit sound like something far more profound than it is. I'm guessing the idea is that this is the "right side" of a NAND gate circuit -- i.e., the output stage.

 

I think it's another case of a contrived example intended to make a simple circuit sound like something far more profound than it is. I'm guessing the idea is that this is the "right side" of a NAND gate circuit -- i.e., the output stage.

He said that the right side is a "nand port", that is a wired name, I think it should be named nand gate and a part of the circuit.

 

Hi...

Our teacher asked us to simulate the right side of a circuit that is a NAND port. That right side of the circuit is attached.
I'm trying to prove with LTSpice that the attached circuit (which is part of a circuit that is supposed to work like a NAND port), knowing that Logic Level 0 is Vce between 0V and 1V and Logic Level 1 is Vce between 4V and 5V, needs to have such a Vbb that makes the transistor work within those limits for Level 0 and Level 1.

So, using the net equations for output and input, I have calculated Ic, then Ib and lastly Vbb for Logic Level 0 and Logic Level 1.

For Logic Level 1 I found Ic=455μA, Ib=2.27μA and Vbb=0.927V
For Logic Level 0 I found Ic=1.83mA, Ib=9.8μA and Vbb=1.61V

But if I try these values for Vbb in LTSpice, the Vbb=0.927V looks like OK because Vce < 1V which is OK for Logic Level 0, but for Vbb=1.61V I should get Vce>4V but LTSpice is outputing a value under 3.8V.

Is there anything wrong with my calcs or can it be due to Vbe of LTSpice to be lower than 0.7V???

Were the resistor values provided, or did you compute them?

It's hard to verify your calculations since you don't provide them.

What you should do is a parametric sweep and take the Vbb source from 0V to 5V.

The logic levels are not defined based on Vce, the are based on the voltage between the output pin and ground. In this case, for that topology and that transistor, these happen to be the same thing. In general they are not.

Input logic levels are not the same as output logic levels. The idea is that if the output, when HI, can produce a voltage all the way down to 4V and still be considered a logic HI, then the input must be able to recognize any voltage above 4V as a logic HI. To ensure that this is the case, the input must be designed so that it will actually recognize voltages that are somewhat below that as a logic HI. Similarly, the input must recognize voltages as being a logic LO that are at least somewhat higher than the highest voltage that an output can generate and still be considered to be at a logic LO.

I'm guess that, for this simple exercise, that is being ignored and a logic LO is being taken as any voltage between 0V and 1V and a logic HI is being taken as any voltage between 4V and 5V, regardless of whether it is an input or an output that is being discussed. Okay, that's fine if that's the case.

So you want to plot Vout vs. Vin and show that for all input voltages that classify as LO, the output classifies as HI and vice-versa.

 

He said that the right side is a "nand port", that is a wired name, I think it should be named nand gate and a part of the circuit.

I think this is just a translation issue. The use of the term "port" confused me, too. It should almost certainly be "the output portion of a NAND gate" (but, of course, it isn't even that, but we can hold our noses and pretend).

 

Hi... Sorry for the translation. Yes, I meant NAND gate. But this is only the right side of the NAND gate circuit, or as you said, the output stage. We were asked to plot the output curve for that part of the whole circuit. The values of resistors Rb and Rc were given values.

What I can't understand is why when Vbb = 0.927V, the Vce isn't above 4V.
The equations I used were:
Vcc = Rc*Ic + Vce
Ib = Ic/β
Vbb=Rb*Ib+Vbe

Logic Level 0 means 0.5V≤Vce≤1V (active region means Vce ≥0.5 and jBE forward biased with Ib≥0), so:
5=2.2*Ic + 1
Ic = (5-1)/2.2=1.82mA

Ib=1.82/200=9.1μA

Vbb=100*9.1+0.7=1.61V

Logic Level 1 means 4V≤Vce≤5V
5=2.2*Ic+4
Ic=(5-4)2.2=455μA

Ib=455/200=2.275μA

Vbb=2.2*455μA + 0.7=0.927V

 

hi psy,
The circuit you have posted is an inverter switch.
The plot I get from your circuit is what I would expect.
Note the transistor turn on threshold and saturation voltages

E

 

hi psy,
The circuit you have posted is an inverter switch.
The plot I get from your circuit is what I would expect.
Note the transistor turn on threshold and saturation voltages

E

Yes, but we are being asked for what Vbb we will have the transistor working as an inverter within the limits our teacher gave us for Vce of 0V up to 1 V being logic Level 0 and from4V u to 5V being Logic Level 1.

 

With that basic circuit you cannot have Vce of 0V, with a Base Vbb of 0V to 1V.
Vbb=0 will always mean that Vce = 5V and if Vbb=1 then Vce =0,, when using a NPN transistor.

 

With that basic circuit you cannot have Vce of 0V, with a Base Vbb of 0V to 1V.
Vbb=0 will always mean that Vce = 5V and if Vbb=1 then Vce =0,, when using a NPN transistor.

Well, I just don't know what to do then. How am I going to answer to my teacher what he asked?
I have no idea!
He asks for what values of input we can still consider Logic Level 1 in the output???
And for what values of input we can still consider Logic Level 0 in the output???

So, for Logic Level 1, Vout (that I assume to be the same as Vce, or will it be Vcol??) must be greater than 4V and for Logic Level 0, the same output voltage must be lower than 1V.
So I used this values for Vce to calculate Vbb...

Have you seen my calcs?

 

You were asked to plot the output curve for that circuit, so plot the output curve. What you posted is NOT the output curve.

An output curve has the output voltage on the Y-axis and the input voltage on the X-axis. Plot that curve and the answers will be very evident.

I don't see that you are being asked to calculate anything. Run the simulation and plot the output curve.

 

You were asked to plot the output curve for that circuit, so plot the output curve. What you posted is NOT the output curve.

An output curve has the output voltage on the Y-axis and the input voltage on the X-axis. Plot that curve and the answers will be very evident.

I don't see that you are being asked to calculate anything. Run the simulation and plot the output curve.

WBahn, in this problem we were not asked to plot the output curve but to demonstrate for which values of Vbb, the transistor will be working as an inverter, assuming that Logic Level 0 is when output is lower than 1V and Logic Level 1 when output is greater than 4V...

I just wanted to demonstrate that in LTSpice.

 

WBahn, in this problem we were not asked to plot the output curve but to demonstrate for which values of Vbb, the transistor will be working as an inverter, assuming that Logic Level 0 is when output is lower than 1V and Logic Level 1 when output is greater than 4V...

I just wanted to demonstrate that in LTSpice.

You need to make up your mind: Post #7 "We were asked to plot the output curve for that part of the whole circuit."

But whether you are asked to do it or not, if you plot the output curve, you will be able to answer the question of which values of Vbb satisfy the specs by inspection.

 

You need to make up your mind: Post #7 "We were asked to plot the output curve for that part of the whole circuit."

But whether you are asked to do it or not, if you plot the output curve, you will be able to answer the question of which values of Vbb satisfy the specs by inspection.

Ok, probably I haven't used the correct words to express myself. My apologies. What I meant was to do what I said in my last post. Can you state again how should I do it in LTSpice?

 

Your final calculations are correct but the main problem with your calculations is that you have wrongly assumed that beta and Vbe is constant, witch is not true.

 

Your final calculations are correct but the main problem with your calculations is that you have wrongly assumed that beta and Vbe is constant, witch is not true.

Ok, I'll write a note telling that attached to the simulation!
Thanks

 

Ok, probably I haven't used the correct words to express myself. My apologies. What I meant was to do what I said in my last post. Can you state again how should I do it in LTSpice?

Have you made ANY attempt to use the LTSpice User's Guide?

 

Ok, I'll write a note telling that attached to the simulation!
Thanks

Be sure to properly credit the note to Jony130, since this information in no way came about as a result of YOUR efforts.

 

Ok, now about the whole circuit, the NAND gate, there is a diode with it's anothe connected to the transistor's base. Can you explain me the importance of this diode?