I want to run more than one process in parallel in the same CPLD (MAX II EPM240 CPLD) and I did it as shown in the following VHDL code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity final is
port(   clk_in_for_fixed,clk_in_for_programmable,xor_in_1,xor_in_2,not1_in1,not2_in2: in std_logic;
        clk_out_fixed, clk_out_programmable,xor_out,not1_out,not2_out: out std_logic;
        programmable_divide_value : in std_logic_vector (9 downto 0)
        );
end final;

architecture Behavioral of final is

signal counter_fixed,counter_programmable,fixed_divide_value,programmable_divide_value : integer := 0;

begin
fixed_divide <= 40;
programmable_divide <= to_integer(unsigned(programmable_divide_value(9 downto 0)));

process(clk_in_for_programmable)
begin

    if( rising_edge(clk_in_for_fixed) ) then
        if(counter_fixed < fixed_divide/2-1,) then
            counter_fixed <= counter_fixed + 1;

             fixed_clk_out <= '0';
        elsif(counter < fixed_divide-1) then
            counter <= counter + 1;
            fixed_clk_out <= '1';
        else
             fixed_clk_out <= '0';
            counter_fixed <= 0;
        end if;
    end if;
end process; 

 if( rising_edge (clk_in_for_programmable) then
        if(counter_programmable< programmable_divide/2-1) then
            counter_programmable <= counter_programmable+ 1;
             clk_out _programmable<= '0';
        elsif(counter_programmable< programmable_divide-1) then
            counter_programmable <= counter_programmable+ 1;
             clk_out _programmable<= '1';
        else
            clk_out_programmable_<= '0';
            counter_programmable_ <= 0;
        end if;
    end if;

end process;   

end Behavioral;

Is this the correct method to run processes in parallel in the same CPLD/FPGA?

 

Not really. First of all, behavioral architecture is meant for test benches, not for the actual implementation, you should use RTL instead. Second, you are missing another process declaration after the first end process.

I think you should try to simulate your code and see if it does compile and if it does what you intended.

 

Not really. First of all, behavioral architecture is meant for test benches, not for the actual implementation

What? Does behavioral architecture not applicable for actual implementation?

you are missing another process declaration after the first end process.

All the processes in the code shown above should be run in parallel. So, do I need process declaration after the first end process?

Compilation was successful. But I didn't simulate it yet.

 

All processes are executed in parallel and each process needs its own sensitivity list.
I am not exatly sure with the behavioral architecture, so just try simulating it and see if it works or not. Also see this http://www.freerangefactory.org/dl/free_range_vhdl.pdf

 

You should have seperate "process" statements for your two processes. I doubt your code will compile as you've written it. Actually, there is no problem using two "if" clauses in the same process, but they would need to use the same clock, and the "end process" statement before the 2nd one is an error. Better to make two processes each with it's own sensitivity list. Don't worry about the behavioral thing; modern compilers work just fine with this style.

 

You should have seperate "process" statements for your two processes. I doubt your code will compile as you've written it. Actually, there is no problem using two "if" clauses in the same process, but they would need to use the same clock, and the "end process" statement before the 2nd one is an error. Better to make two processes each with it's own sensitivity list. Don't worry about the behavioral thing; modern compilers work just fine with this style.

I modified the code. Are there any thing to be modified further?

library IEEE;
 use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.NUMERIC_STD.ALL;  
entity final is 
port(   clk_in_for_fixed,clk_in_for_programmable,xor_in_1,xor_in_2,not1_in1,not2_in2: in std_logic;         
clk_out_fixed, clk_out_programmable,xor_out,not1_out,not2_out: out std_logic;         
programmable_divide_value : in std_logic_vector (9 downto 0) 
        ); 
end final;  

architecture Behavioral of final is  
signal counter_fixed,counter_programmable,fixed_divide_value,programmable_divide_value : integer := 0; 

begin 
fixed_divide <= 40; 
programmable_divide <= to_integer(unsigned(programmable_divide_value(9 downto 0)));  

process(clk_in_for_fixed) 
begin      
if( rising_edge(clk_in_for_fixed) ) 
then         if(counter_fixed < fixed_divide/2-1,) 
then             counter_fixed <= counter_fixed + 1;               fixed_clk_out <= '0';         
elsif(counter < fixed_divide-1) then             counter <= counter + 1;             fixed_clk_out <= '1';         
else              fixed_clk_out <= '0';             counter_fixed <= 0; 
        end if;     
end if; 
end process;  

process(clk_in_for_programmable) 
begin   
if( rising_edge (clk_in_for_programmable) 
then         if(counter_programmable< programmable_divide/2-1) 
then             counter_programmable <= counter_programmable+ 1;              
clk_out _programmable<= '0';         elsif(counter_programmable< programmable_divide-1) 
then             counter_programmable <= counter_programmable+ 1;              clk_out _programmable<= '1';
else             clk_out_programmable_<= '0';             counter_programmable_ <= 0; 
        end if;
end if;  
end process;     

end Behavioral;

 

I modified the code. Are there any thing to be modified further?

Using code tags instead of quote tags makes this much easier to read and analyze.