RF Chokes

Thread Starter

PRS

Joined Aug 24, 2008
989
I've always wondered what constitutes the appropriate value of inductance for an RF choke. It is different at different frequencies. The reactance is given as....

XL = 2*pi*f*L

... meaning the same inductor has a higher reactance at higher frequencies. In many cases a choke is used to bias a transistor's collector but keep the signal off the power source's rail. This is done by XL. What is a high enough XL? 5K? 10K? ..... 100K?
 

wmodavis

Joined Oct 23, 2010
739
There is no "appropriate value of inductance for an RF choke" that is dependent only upon frequency.

Frequency is not the only or main parameter to consider.

It mostly depends on the application and the impedance of the circuit you are trying to protect or enhance the operation of.
 

Thread Starter

PRS

Joined Aug 24, 2008
989
There is no "appropriate value of inductance for an RF choke" that is dependent only upon frequency.

Frequency is not the only or main parameter to consider.

It mostly depends on the application and the impedance of the circuit you are trying to protect or enhance the operation of.
As I see it radio is a science, not magic. There must be a specific value of XL that is sufficient to keep the signal off the supply while at the same time not so large as to create parasitic capacitance that will defeat the purpose of the choke.
 

Thread Starter

PRS

Joined Aug 24, 2008
989
+1

That is correct. Add R or C into your formula to make a meaningful application.
The case I usually encounter is where the choke is in series with the collector with respect to the supply. This collector usually has 2pF capacitance to ground. I work MF and HF. At the lower end of this range 2pF is insignificant. On the other hand the load often has 30 pF
to ground. I'm not intentionally creating a tank, but there must be one at the point where XL = Xc, which lies above my signal frequency. In view of this, is there any reason not to just make the tank have an XL of 10K? This should knock the signal current reaching the supply down by four orders of magnitude, shouldn't it?
 

wmodavis

Joined Oct 23, 2010
739
As I see it radio is a science, not magic. There must be a specific value of XL that is sufficient to keep the signal off the supply while at the same time not so large as to create parasitic capacitance that will defeat the purpose of the choke.
Electronics IS a well developed science. I agree wholeheartedly. True science requires taking all pertinent facts into account. Rules of thumb usually only touch the surface and lead many people to decide it IS magic because so much of the scientific principals get left out and the rules do not always apply therefore leading to confusion. But I hope your search leads you to the appropriate inductance and beyond that the knowledge of when it is NOT apporopiate and why.
 

t_n_k

Joined Mar 6, 2009
5,455
The case I usually encounter is where the choke is in series with the collector with respect to the supply. This collector usually has 2pF capacitance to ground. I work MF and HF. At the lower end of this range 2pF is insignificant. On the other hand the load often has 30 pF
to ground. I'm not intentionally creating a tank, but there must be one at the point where XL = Xc, which lies above my signal frequency. In view of this, is there any reason not to just make the tank have an XL of 10K? This should knock the signal current reaching the supply down by four orders of magnitude, shouldn't it?
It's unclear what you are referring to here. Is this an RF power amplifier stage? Is the inductor the collector load?? Perhaps a schematic would be more informative as well.
 

Thread Starter

PRS

Joined Aug 24, 2008
989
Here's an example of a schematic. Notice it gives all of the component values except for the two chokes. The circuit is that of an FM modulator having a center frequency of about 10 MHz. With this in mind what is the optimum value of L for the choke at the drain and why? And while we're at it what is the best value of L for RFC2? From Bertus's link the rule of thumb would be hundreds of microhenries ( from Table II). But I'm trying to quantify the optimum value based on math. Any help will be greatly appreciated. ;)
 

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Thread Starter

PRS

Joined Aug 24, 2008
989
Electronics IS a well developed science. I agree wholeheartedly. True science requires taking all pertinent facts into account. Rules of thumb usually only touch the surface and lead many people to decide it IS magic because so much of the scientific principals get left out and the rules do not always apply therefore leading to confusion. But I hope your search leads you to the appropriate inductance and beyond that the knowledge of when it is NOT apporopiate and why.
I gave an example circuit down below. Please take a look and give me your thoughts.
 

t_n_k

Joined Mar 6, 2009
5,455
Thanks for posting the example schematic.
Looks like a variable frequency [FM] Clapp oscillator with the varactor diode as the additional Clapp capacitor. The capacitive divider [C1 & C2] feedback tap is connected to the source terminal. As an aside comment, I would think the FET gate should be capacitively bypassed to ground to form a common gate topology. Alternatively delete R1 [100k] and directly ground the gate terminal. Otherwise the circuit may not oscillate.

RFC1 is the drain load choke which (by the way) doesn't prevent AC current [signal component on DC component] flowing into the positive DC bus [VDD+]. It's a load impedance which impacts overall loop gain to enable oscillation. The choke value can vary over a substantial range before things change dramatically. The smaller the RFC1 inductance the lower the drain output voltage. Good design would probably include ensuring the resonance point of RFC1 with Cc1 lies well below the nominal oscillation frequency - say an order of magnitude less. I guess one could go on increasing the choke inductance within the practical physical & electronic limitations. A primary electronic limitation to maximum inductance would include a consideration of the self-resonant frequency of the RFC. Another may include the losses in the RFC at the designed operating conditions.

In summary I would suggest the role of the RFC has to be considered in relation to the rest of the circuit (including parasitic elements), having regard to the overall design intent and associated constraints. I don't know if an optimum value for the RFC exists or is even a particularly noteworthy consideration. Perhaps more to the point - what does optimum mean? Signal harmonic distortion negligible [-xdB]? Maximum signal amplitude? Maximum circuit efficiency for given output loading?

Every design involves compromises and trade-offs. In fact I would suggest one doesn't necessarily want to make an overall design too dependent on the value and quality of one particular component, on which the end product is over reliant in meeting specification.
 
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t_n_k

Joined Mar 6, 2009
5,455
It's also perhaps worth noting in passing that RF chokes have an ultimate limitation as the frequency of operation extends to the point where circuit conductor lengths become comparable with the wavelength - at which point designers may dispense with conventional chokes for signal / bias separation and make use of things like quarter wave [PCB trace] transmission lines for DC bias / power feeds.
 
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Thread Starter

PRS

Joined Aug 24, 2008
989
Thanks for posting the example schematic.
Looks like a variable frequency [FM] Clapp oscillator with the varactor diode as the additional Clapp capacitor. The capacitive divider [C1 & C2] feedback tap is connected to the source terminal. As an aside comment, I would think the FET gate should be capacitively bypassed to ground to form a common gate topology. Alternatively delete R1 [100k] and directly ground the gate terminal. Otherwise the circuit may not oscillate.
You may well be right about the gate needing a ground. The author of the book I got this from was an excellent instructor but very absent minded. His book could not have been proof read by a competent reader; way too many mistakes for that.

RFC1 is the drain load choke which (by the way) doesn't prevent AC current [signal component on DC component] flowing into the positive DC bus [VDD+]. It's a load impedance which impacts overall loop gain to enable oscillation.
I began wondering about that for the last couple of days. My concern there was the idea that the positive supply node was more apt to be a feedback path than it really is. When a voltage source is connected to a circuit either its positive or its negative terminal can be declared the ground. To an AC signal both are considered ground potential but this is not necessarily true. The source has its own internal resistance. Then on the board layout the positive feeds a length of copper, which is not a pure conductor, and the longer this path to our connection point the more resistance and stray capacitance shows up at the positive node of a circuit such as this FM modulator sees. This means that it becomes a potential feedback path for the signal and so we must keep the signal off of it as much as we are able. One way of doing this is a 100 ohm resistor with a .1 or .01 uF capacitor dumping the signal to ground. Now why is it that the ground side of the source can be assumed to be an unpolluted node? I don't think it can be. This is why we make our ground plane as large as possible. Evidently the signal current needs a big sink in order to be truly at the potential of the side of the source we chose to be ground. Conversely, it would be a good idea in large circuits to run a sizable wire directly from the source to a point where ac leakage might occur -- such as the other side of that RFC choke as per the diagram. Does all this make sense? These are just my thoughts on proper board construction.



The choke value can vary over a substantial range before things change dramatically. The smaller the RFC1 inductance the lower the drain output voltage. Good design would probably include ensuring the resonance point of RFC1 with Cc1 lies well below the nominal oscillation frequency - say an order of magnitude less. I guess one could go on increasing the choke inductance within the practical physical & electronic limitations. A primary electronic limitation to maximum inductance would include a consideration of the self-resonant frequency of the RFC. Another may include the losses in the RFC at the designed operating conditions.

In summary I would suggest the role of the RFC has to be considered in relation to the rest of the circuit (including parasitic elements), having regard to the overall design intent and associated constraints. I don't know if an optimum value for the RFC exists or is even a particularly noteworthy consideration. Perhaps more to the point - what does optimum mean? Signal harmonic distortion negligible [-xdB]? Maximum signal amplitude? Maximum circuit efficiency for given output loading?
Good points. I do understand the reason for the choke -- allowing dc to pass while blocking the ac signal, but as you said, it's about keeping the signal where it needs to be and not about preventing ac current from getting on the "positive" voltage line. Nevertheless we do need to keep the signal off the positive line for reasons stated above. And it could be that an RC filter would serve well for this purpose, as described above.


Every design involves compromises and trade-offs. In fact I would suggest one doesn't necessarily want to make an overall design too dependent on the value and quality of one particular component, on which the end product is over reliant in meeting specification.
I think you're right.
 

Thread Starter

PRS

Joined Aug 24, 2008
989
It's also perhaps worth noting in passing that RF chokes have an ultimate limitation as the frequency of operation extends to the point where circuit conductor lengths become comparable with the wavelength - at which point designers may dispense with conventional chokes for signal / bias separation and make use of things like quarter wave [PCB trace] transmission lines for DC bias / power feeds.
I used to work for Systron Donner in Sylmar California. We made electronic test equipment, and rf products in UHF and above. I have seen some really bizarre looking circuits in the microwave range. At those frequencies the capacitors, and resistors are but wee chips and filters were microstrips. We had assemblers working in an air tight room where they had to wear protective gear and slippers and had to take this off when they took breaks. They used microscopes to put the circuits together. "What hath God wrought?!" ;)
 

t_n_k

Joined Mar 6, 2009
5,455
I began wondering about that for the last couple of days. My concern there was the idea that the positive supply node was more apt to be a feedback path than it really is. When a voltage source is connected to a circuit either its positive or its negative terminal can be declared the ground. To an AC signal both are considered ground potential but this is not necessarily true. The source has its own internal resistance. Then on the board layout the positive feeds a length of copper, which is not a pure conductor, and the longer this path to our connection point the more resistance and stray capacitance shows up at the positive node of a circuit such as this FM modulator sees. This means that it becomes a potential feedback path for the signal and so we must keep the signal off of it as much as we are able. One way of doing this is a 100 ohm resistor with a .1 or .01 uF capacitor dumping the signal to ground. Now why is it that the ground side of the source can be assumed to be an unpolluted node? I don't think it can be. This is why we make our ground plane as large as possible. Evidently the signal current needs a big sink in order to be truly at the potential of the side of the source we chose to be ground. Conversely, it would be a good idea in large circuits to run a sizable wire directly from the source to a point where ac leakage might occur -- such as the other side of that RFC choke as per the diagram. Does all this make sense? These are just my thoughts on proper board construction.
You make some important points here. Supply decoupling is always a design consideration - particularly when high rate of change load currents interact with feed-in conductor stray lead inductances. Problems can arise particularly for active devices sitting at the more remote supply take-off points along a single power conductor path or PCB trace with multiple supply take-offs. The virtual mandatory close-proximity capacitive de-coupling of TTL logic chip power lines comes to mind.

Most experienced designers will have these matters in mind - hopefully! Particularly when dealing with signals having associated sharp current changes or wide bandwidth components.

Again, as you mention one must consider to what point or region the de-coupling occurs - usually an effective ground plane. The lack of good signal grounding is also potentially a minefield for the unwary with common-mode signal and earth loop problems leading to potentially frustrating days & sleepless nights.
 

vk6zgo

Joined Jul 21, 2012
677
Thanks for posting the example schematic.
Looks like a variable frequency [FM] Clapp oscillator with the varactor diode as the additional Clapp capacitor. The capacitive divider [C1 & C2] feedback tap is connected to the source terminal. As an aside comment, I would think the FET gate should be capacitively bypassed to ground to form a common gate topology. Alternatively delete R1 [100k] and directly ground the gate terminal. Otherwise the circuit may not oscillate.

RFC1 is the drain load choke which (by the way) doesn't prevent AC current [signal component on DC component] flowing into the positive DC bus [VDD+]. It's a load impedance which impacts overall loop gain to enable oscillation. The choke value can vary over a substantial range before things change dramatically. The smaller the RFC1 inductance the lower the drain output voltage. Good design would probably include ensuring the resonance point of RFC1 with Cc1 lies well below the nominal oscillation frequency - say an order of magnitude less. I guess one could go on increasing the choke inductance within the practical physical & electronic limitations. A primary electronic limitation to maximum inductance would include a consideration of the self-resonant frequency of the RFC. Another may include the losses in the RFC at the designed operating conditions.

In summary I would suggest the role of the RFC has to be considered in relation to the rest of the circuit (including parasitic elements), having regard to the overall design intent and associated constraints. I don't know if an optimum value for the RFC exists or is even a particularly noteworthy consideration. Perhaps more to the point - what does optimum mean? Signal harmonic distortion negligible [-xdB]? Maximum signal amplitude? Maximum circuit efficiency for given output loading?

Every design involves compromises and trade-offs. In fact I would suggest one doesn't necessarily want to make an overall design too dependent on the value and quality of one particular component, on which the end product is over reliant in meeting specification.
I don't see how you can call RFC1 the "drain load choke".

The drain load is effectively,that of the LC resonant circuit.
The value of RFC1 is such that its reactance is high enough at the design frequency,that its presence in parallel with the LC network will have a negligible effect upon the load impedance.

Pray tell me how a high Inductive Z component does not "prevent "(OK,let's say substantially inhibit) signal currents flowing into the
Vdd + line?
The Vdd supply is unlikely to look like a perfect short circuit to signal Earth,& any RF signal on a supply line which feeds other stages can cause major instability.

This oscillator circuit is (as are all 3 terminal LC oscillators) a special case of an RF Amplifier--in this case,of the Shunt fed variant.
"Googling" for "Shunt fed RF Amplifiers" brings up a number of sites,of lesser & greater usefulness.
Most of them are based on Vacuum Tube designs,but the basics remain the same.
This one is interesting,in that he goes into some of the points you raised.

http://www.w8ji.com/rf_plate_choke.htm
 

alfacliff

Joined Dec 13, 2013
2,458
there is no normal value for rf chokes, but a good rule of thumb is 10 times the impedance of the circuit. such as a Z of 100 ohms for a circuit impedance of 10 ohms.
 

BR-549

Joined Sep 22, 2013
4,928
VK6ZGO...I like the way you talk. Do they teach tube circuits in school any longer? I was taught tubes first, then transistors. We had to build and analyse all kinds of tube circuits before we studied transistors. Then the difference between voltage and current devices could be compared. But the circuit principles are the same. They are probably using terms I haven't even heard of to explain transistor operation now. Oh well.....they were always screechy.
 
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