Resources on switch node jitter for a DC/DC converter

Thread Starter

BitsNBytes

Joined Mar 22, 2021
37
Hello Everyone,

I am looking for resources that discuss system level concerns regarding switch node jitter for a DC/DC converter. I can find mentions on TI's E2E forum, but almost, if not all, are simply references to those posting measurements on their parts. The search for 'jitter' will inevitably bring up jitter in regards to clocks and sample systems. Since no one uses the switch node of a buck/boost/buck-boost etc. for a clocking system then what would someone be concerned with in regards to 'excessive' switch node jitter?
I have not been able to find in depth discussion on switch node jitter (the voltage switch node, the inductor current waveform) and why it is crucial for any engineer to be concerned about. I could see no engineer would want switch node jitter to be 25% or more of the on (or off time) of the converter, but what else does this manifest as in a system?
Output voltage ripple? Small signal stability? Spectral noise (perhaps phase noise) when using a converter to power an RF type source?
 

Papabravo

Joined Feb 24, 2006
21,261
What makes you think it is a significant problem? If DC-DC converters were running open loop then maybe, but most if not, all have closed loop compensated controls that are capable of meeting very tight specifications for current and voltage ripple. It would not be difficult to use an FM VCO to investigate the effects of frequency variation in the clock source. My guess is that you might have a hard time measuring the effect.

OTOH, I could be wrong. What do you know about simulating DC-DC converters?
 

crutschow

Joined Mar 14, 2008
34,684
As you noted, the only reason I can think of where clock jitter would be a concern is if the EMI frequency interfere with some RF receiver.
 

Thread Starter

BitsNBytes

Joined Mar 22, 2021
37
What makes you think it is a significant problem? If DC-DC converters were running open loop then maybe, but most if not, all have closed loop compensated controls that are capable of meeting very tight specifications for current and voltage ripple. It would not be difficult to use an FM VCO to investigate the effects of frequency variation in the clock source. My guess is that you might have a hard time measuring the effect.

OTOH, I could be wrong. What do you know about simulating DC-DC converters?
I am suspicious that it is an actual problem. Voltage ripple is a function of inductor current ripple and by extension the actual inductor value along with output capacitor values. I can see that jitter would be a component of this as well, but second order. Looks like I have some bench work to do even if it is a personal curiosity and say, "Yeah, nah. Don't worry about this."
I would expect (excessive) jitter of the switch node to have literature on the subject, but it has been elusive.

Here is a TI application note:
https://www.ti.com/lit/pdf/slua747

This has a good overview of why jitter happens in the first place with a buck converter (voltage or current mode). Not so much on why someone would try to argue that it is so detrimental in a generalized system.

As you noted, the only reason I can think of where clock jitter would be a concern is if the EMI frequency interfere with some RF receiver.
This seems most likely IMO.
 

MisterBill2

Joined Jan 23, 2018
18,977
Is this jitter problem present in an actual physical hardware circuit? Or is it in a simulation? AND, importantly, is this for a product, or a "one off" build of a single assembly?
Production fixes have to be far broader because every package has a stack-up of all the component variables.
Been down that road a few times.
 
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