Hi,

In this article near the bottom there's FIR filter. I'd like to understand how the resistor values are calculated.
Schematic

When I naively do 26.75k/sinc I get roughly the right values but not quite good enough. Any ideas on how this is done?

 

I would write back to the author and ask directly the question.
As a former one who wrote many technical articles, I can tell you that authors love reader’s feedback and questions.

 

Thanks for the suggestion @schmitt trigger , I may do that if I can find the proper channel.

 

From the previously referenced article and this article I put together the attached circuit.

The clock is there but the pseudo-random bit sequency is not. All shift register outputs are high. I assume all outputs start low. Then R3 will pull pin 14 of U2 high and 1s start filling the shift registers until output QB1 of U5 becomes high and XOR U1C switches high until output QG of U5 also becomes high. Then U1C switches low and the sequence should be on its way(?), but it's not.

I tried to simulate what happens around R3 / C4, see prbs_init. Without the diode the data input (pin 14 of U2) never goed low. With the diode it does. But then it occured to me there must be a protection diode at that does exactly the same thing as D2 in the sim. So in order not to make bad things worse I haven't yet tried to botch in a diode parallel to R3 in the schematic.

I tried inserting ground potential at TP6. Then when I untie TP6 from ground I see a very short glitch going high at TP5 before everything latches again.

TLDR;
Any ideas why the sequence won't start and how I can make it start?

Edit: I see now that I daisy-chained the shift registers incorrectly ...
Edit2: With the botch wires in place it's still not working, all outputs latched high.

 

Don’t you have to seed the shift registers?

 

Then circuit on the reset pin forces all outputs to zero. From that point it will continue to work. IC4 form an exclusive nor gate, which will output a 1 if its inputs are zero, so it can't get stuck at all zeroes. However, if the feedback from IC4 is wrong it will get stuck at all 1s.
The resistor values are the reciprocal of the FIR coefficients. Only their ratios matter. Choose a values for the largest weight which will be the smallest resistor and choose a value that a CMOS gate could happily drive. Then calculate all the other values from that one.

 

Don’t you have to seed the shift registers?

I think the RC around the serial data in (pin 14 of U2) will seed the 74HC595s with 1s. But I never reset them so I suppose they could initialize with any data.
My circuit uses the XOR feedback network from Rod Elloitts version. Now that I better understand what's going on I think I like the XNOR network by Art Pini better as it doesn't need a capacitor. That might make it better suited for an adjustable clock frequency.

The resistor values are the reciprocal of the FIR coefficients.

What I didn't know previously is that a window function or some other modifier can be applied to the coefficients and thereofore I wasn't able to recover the resistor values straight from the sinc function.

With a clock of around 60kHz and a 33uF feedback capacitor there is some sign of the bit stream. When I briefly connect TP6 to the clock the PRBS starts until it stops after a few seconds. In the video linked below I do this twice, resulting in different sequence lengths.

The video shows the output at TP5 with an external trigger on the clock.
https://www.youtube.com/shorts/-DUboDKHuvU

 

If you've got 74HC595s, have you got all the latches connected correctly? You would be better off with 74HC164.

 

In the circuit diagram of post #4, "white_noise_generator.png", I think I may have had the daisy-chaining wrong so I reworked the board to the image attached below. So that's chaining from pin 9 instead of pin 7.

If you've got 74HC595s, have you got all the latches connected correctly?

Are you referring to the output enable? They are tied to ground, i.e. enabled. The datasheet says this makes the shift register one clock cycle ahead of the storage register. I think that should be ok.

You would be better off with 74HC164.

Thanks, I'll have a look.

 

Here's a revision with the 74HC164. I changed the seeding from 1s to 0s and got rid of the capacitor in the feedback path. Any thoughts on the current scheme would be appreciated.

I would like to add a variable level shifter on the output, something like the attached LTSpice simulation. Seems like it would work but any thoughts on that? I'm not so sure what the optimal resistor values are here. Are the 10k ok, should they be lower/higher? Other things?

 

I ran into something similar before - it’s not just a straight R = constant / sinc(x) thing. That only gets you in the ballpark.

 

I ran into something similar before - it’s not just a straight R = constant / sinc(x) thing. That only gets you in the ballpark.

Yes. After encountering this I studied low pass digital filters for a bit. It's common to apply a window function on top of the sinc function. There are numerous window functions and I suppose that Art Pini applied one of these functions. So I picked one that I like and applied it. It's not going to be super critical anyway.

I'm now going ahead with the schematic from post #10 with the level shifter tacked on and see if the bit stream runs continuously this time.