Relocating an IO section - addressing (moot)

Thread Starter


Joined Oct 25, 2020
Some context (if desired) - otherwise jump down to the "tl;dr" notation further down.

This ongoing project of mine has 5 boards: Power, Analog, Logic, Interface, and Display.

The Interface board has three main roles: the upper 128 bytes of RAM (of 256 total bytes), a set of inputs, and the support circuitry to interface the 8279 display / keyboard IC on the display board with the core system.

The core portion of the system was that which centered on the 'custom' SC44125 MPU (a version of the MC6801 apparently designed and produced for the automotive market). After dinking around off and on for some time, I settled on the 68HC11F1 as a replacement for the SC44125 (the only thing that must change is the memory map, so the firmware has to be recompiled).

Since the 'HC11 has 1K of on-board RAM, I was able to eliminate the MC6810 and HM-6561 SRAMs from the Logic and Interface boards (they're hard to find these days anyway and replacing them with 6116s was a waste).

I then realized it didn't make much sense for the Interface board to have all that hardware to support 9 inputs when I was only using 4 of the 16 I/O pins on the MC6821 PIA, so the inputs were migrated to the Logic board (might as well, since the firmware has to be redone anyway).

What remains is the schematic below, the bulk of which is apparently buffering to clean up the signals between the interface / display boards and the core system, since the interconnection is 1' of unshielded ribbon cable. This buffer section is everything to the left of the dashed line.

The 50-pin ribbon cable connector links the interface board to the display board, and it at least has the signals interleaved with lines tied to ground.

Next up, the signals that continue into the 8279:

EIRQ: One of the relocated inputs (a signal to indicate a key has been pressed)

RST: Reset line - for some reason the reset line on the 8279 is active high.

RD / WR: Again, the 8279 breaks convention and has separate Read and Write lines.

ED0 - ED7: System data bus, and which needs no further explanation or changes.

Clk: The original design had the system clock passing through a latch wired 'always on'.
I'm not sure why there was even a latch on the clock line, so I swapped it for a spare
OR gate, as the propagation delay was similar. I can post a snippet showing the latch if desired.

The CS line is the chip select, and which is active low as would be expected.

If you're in a "tl;dr" mood, start reading here.

The last signal into the 8279, the A00 line, puts the 8279 into command or status mode.
Low: Status mode / send or receive data to system
High: Receive commands from the system

The 8279 is currently configured so that it can be accessed via two memory addresses:

0x0CFE, which is the data port
In read mode, it presents the keyboard data (matrix code for last key pressed).
In write mode, it accepts the data to be written into the display buffer.

0x0CFF, which is the command port

I need to relocate the A00 and CS lines from 0x0CFE / 0x0CFF to 0x2800 / 0x2801, but I'm having trouble visualizing how to go about changing the addressing, because of the 74LS138.

I already have a signal on the Logic to select the relocated IO space (2xxx), so that's a start.

If I can get the logic for A00 and CS ironed out, I can finish consolidating the right-hand portion into the Logic board and eliminate the Interface board completely...


Thread Starter


Joined Oct 25, 2020
This is what I worked out on my own... would appreciate another set of eyes on this if possible.

If the addressing looks good, then this section of the redesign is essentially complete and I can move on to developing the Arduino / LCD replacement of the display board.

Edit: There was still one hiccup, which has now been vanquished.


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