I have attached the circuit in a PNG file below. I'm confused about what exactly is the bottom wire that connects to all the T flip Flops ( the output that is produced by the NAND gate at the end of the T flip flop sequence and fed into the bottom of each T flip flop, with the bubble on the end)
Is this representative of the load being fed into the circuit, or the common clear signal( Clr)....I can't really tell which it would be, could anyone clarify? Otherwise I can't really solve this problem.
Is this representative of the load being fed into the circuit, or the common clear signal( Clr)....I can't really tell which it would be, could anyone clarify? Otherwise I can't really solve this problem.
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