Hi all,
I was reading the article in the link below, where it says:
"Because the D-type flip-flop does not have a hold mode and will always cause the copying of its D inputs to the Q outputs on every clock pulse, we gate the clock (not nice) to allow conditional load of the register."
Why is it 'not nice' to use such layout?
http://faculty.kfupm.edu.sa/coe/ashraf/RichFilesTeaching/COE022_200/Chapter 5.htm
Thanks in advance.
I was reading the article in the link below, where it says:
"Because the D-type flip-flop does not have a hold mode and will always cause the copying of its D inputs to the Q outputs on every clock pulse, we gate the clock (not nice) to allow conditional load of the register."
Why is it 'not nice' to use such layout?
http://faculty.kfupm.edu.sa/coe/ashraf/RichFilesTeaching/COE022_200/Chapter 5.htm
Thanks in advance.