Hi everyone, I have a question.
as part of a project I'm working on, I have a register file- an array of 32 registers.
There are input signals of RegDest- a 5 bits signal which tells which register to write to, Data - a signal of the data that need to be saved at RegDest, and another input signal of RegSource - 5 bits which reads the data from RegSource
The output is the data which is read from RegSource.
now, the problem rises if RegSource == RegDest, I solved it with a bypass- a mux before the output that checks if RegSource == RegDest, and if so, takes the Data input signal.
now I have been asked to solve the problem without a bypass- the solution I mentioned above and I don't have another idea.
I'll be glad for help
thanks
as part of a project I'm working on, I have a register file- an array of 32 registers.
There are input signals of RegDest- a 5 bits signal which tells which register to write to, Data - a signal of the data that need to be saved at RegDest, and another input signal of RegSource - 5 bits which reads the data from RegSource
The output is the data which is read from RegSource.
now, the problem rises if RegSource == RegDest, I solved it with a bypass- a mux before the output that checks if RegSource == RegDest, and if so, takes the Data input signal.
now I have been asked to solve the problem without a bypass- the solution I mentioned above and I don't have another idea.
I'll be glad for help
thanks