reading and writing to a register file without bypass

Thread Starter

lidor250

Joined Oct 2, 2021
9
Hi everyone, I have a question.
as part of a project I'm working on, I have a register file- an array of 32 registers.
There are input signals of RegDest- a 5 bits signal which tells which register to write to, Data - a signal of the data that need to be saved at RegDest, and another input signal of RegSource - 5 bits which reads the data from RegSource
The output is the data which is read from RegSource.
now, the problem rises if RegSource == RegDest, I solved it with a bypass- a mux before the output that checks if RegSource == RegDest, and if so, takes the Data input signal.
now I have been asked to solve the problem without a bypass- the solution I mentioned above and I don't have another idea.
I'll be glad for help :)
thanks
 

drjohsmith

Joined Dec 13, 2021
394
Hi everyone, I have a question.
as part of a project I'm working on, I have a register file- an array of 32 registers.
There are input signals of RegDest- a 5 bits signal which tells which register to write to, Data - a signal of the data that need to be saved at RegDest, and another input signal of RegSource - 5 bits which reads the data from RegSource
The output is the data which is read from RegSource.
now, the problem rises if RegSource == RegDest, I solved it with a bypass- a mux before the output that checks if RegSource == RegDest, and if so, takes the Data input signal.
now I have been asked to solve the problem without a bypass- the solution I mentioned above and I don't have another idea.
I'll be glad for help :)
thanks
Post your code please,
 

drjohsmith

Joined Dec 13, 2021
394
I'm just trying to discuss the Logic design of the things...the exact code is not the issue..
Your logic is correct,

but it depends upon the environment

I'd design such one way in an ASIC

another way in a bread board logic chips

another way in a FPGA

another way in an HLS / C++ design environment,

And all of these will depend upon what I have available in the ASIC / FPGA or digital logic chips,

even in logic chips I would do different in PECL as I would in LVCMOS ,

there are also questions such as what to read whilst writing,
byte or bit access controls, single or multi port, et all

To answer any further,
I'd need to know what technology and design tools your looking at
and we could well do this best by you providing an example of the code you have

This is only a simple register you say
so I'd imagine 20 lines of code max , or a A4 schematic .
 

JWHassler

Joined Sep 25, 2013
293
Hi everyone, I have a question.
as part of a project I'm working on, I have a register file- an array of 32 registers.
There are input signals of RegDest- a 5 bits signal which tells which register to write to, Data - a signal of the data that need to be saved at RegDest, and another input signal of RegSource - 5 bits which reads the data from RegSource
The output is the data which is read from RegSource.
now, the problem rises if RegSource == RegDest, I solved it with a bypass- a mux before the output that checks if RegSource == RegDest, and if so, takes the Data input signal.
now I have been asked to solve the problem without a bypass- the solution I mentioned above and I don't have another idea.
I'll be glad for help :)
thanks
The equality of the two addresses could disable something else... read-select, maybe?
I agree with the other folks here: it's hard to give a helpful answer with no more info.
For example, the question immediately had me thinking in Verilog, but would an answer in that language have helped?
 
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