a tricky one, to cut a long story short/ish, ive been working on some badly damaged powered speakers on and off for the last couple of months,
after a lot of work and some great help, these are now working fine,apart from slight pops from the high frequency speakers on power on.
.the LF is good
although the mute delay circuit checks out fine, im getting no delay at all at the mute pin,
this is a similar circuit,



i should be getting a delay of nearly a second before pin 3 reaches 2.7 volts,
thats using an rc calculator,
but a bit of a long shot, what is the effect on the RC constant with
a negative voltage, in this case minus 19 volts,on the cap neg,? rather than the more usual 0 volt.

thank you
dougal


?

 

It is the nature of exponential waveforms that they are insensitive to the absolute voltages, only the difference. In your diagrams you incorrectly imply that the capacitor voltage actually reaches -Vs or -Vs+5. This is not correct. The waveform approaches those values asymptotically, and never actually reaches those values. What expression are you using for voltage as a function of time? For charging, it should be:

\(-V_s + 5(1-e^{-\frac{t}{RC}})\)

For discharging, it should be:

\(-V_s+5(e^{-\frac{t}{RC}})\)

 

thank you for your reply, and apologies for the delay.
i am not very good at maths, i have cheated a bit.

the main question of my post was-
at what time after power on, does the voltage on pin 3 reach the mute threshold of 2.7 volts?
,and am i right in assuming a supply voltage of 24 volts .-19 volts and +5 volts?,

sorry about that,
dougal

 

thank you for your reply, and apologies for the delay.
i am not very good at maths, i have cheated a bit.
View attachment 112850
the main question of my post was-
at what time after power on, does the voltage on pin 3 reach the mute threshold of 2.7 volts?
,and am i right in assuming a supply voltage of 24 volts .-19 volts and +5 volts?,

sorry about that,
dougal

Is that 2.7 volts with respect to Vs=-19VDC or 2.7 volts with respect of 0VDC. Which is it?
Let us assume the former, since that is consistent with the schematic and the graphical picture:

\(-19.5 + 2.7 = -16.8\)

\(-16.8 = -19.5 + 5(1-e^{-\frac{t}{RC}})\)

\(2.7 = 5(1-e^{-\frac{t}{RC}})\)

\(1-\frac{2.7}{5}=e^{-\frac{t}{RC}})\)

\(0.460=e^{-\frac{t}{RC}})\)

\(ln(0.460)=-\frac{t}{RC}\)

\(t= -RC ln(0.460)\)

Using R=22KΩ and C=10 μF gives us

\(t= -(22\; K \Omega )(10\; \mu F)(-0.777)=0.171\; \text seconds\)

Is that the answer you were looking for? Hmmm -- I guess not.
I think your supply voltage for this problem should be considered as -19 VDC to -14VDC aka -Vs + 5

 

But the capacitor in your circuit is 10uF.

 

yes you are quite right, i must get some new glasses.
i have reset the calculator to 10uf which gives 26 milliseconds, still far short of the second or so needed,

 

View attachment 112851
But the capacitor in your circuit is 10uF.

What's a factor of 2 when you're looking for precise answers to 6 significant figures.

 

yes you are quite right, i must get some new glasses.
i have reset the calculator to 10uf which gives 26 milliseconds, still far short of the second or so needed,

I think you are still using the wrong supply voltage. You have chosen to supply a fragment of the original schematic. This fragment is missing the critical information we need to answer your question. What is the supply voltage for the chip that pin 3 is attached to?

 

i apologise for the lack of info, happy to correct,
http://www.silicon-ark.co.uk/datasheets/tda2052-datasheet-st.pdf

the bottom pic is the power supply rails for this chip.


when i said the board componants etc checked out with the dmm, i couldnt test the cap.
but it didnt appear shorted...

 

as a matter of interest,ive just used the rc calculator on the low frequency chip, which is almost identical ,
and uses the same mute signal, but uses ground or zero volts as the cap neg, still only 152 milliseconds,
but in practise its working fine with a good 1 second delay.

im baffled, might be one to live with,...?

 

as a hobbyist, im well out of my depth on this, but is a favour for a good friend, and i didnt want the aac experts spending too much of their time on this,
however if anyone has the time and enjoys a challenge, this is the full schematic.
http://music-electronics-forum.com/attachments/33751d1430277257-svparts_rp6g2scha1.pdf
scroll down to bottom.

the opamp circuit that provides the mute voltage checks ok,(with thanks to joe). as the LF also uses this circuit and is fine with a good delay.

note-.the limiter circuit on page 17 is not included on the actual boards.

 

OK. So the small block labeled "MUTE/ST-BY" is actually inside another chip. Now if the play node is actually at "-Vs+5" and -Vs=-19.5 Volts, then play should be at -14.5 volts. That circuit should be equivalent to one that works from 0 to 5 volts as indicated in my post number #4. I can go back and correct the calculation for Vs=-19.5V in the first two lines and the rest remains the same. This shows that the actual value of -Vs, at the chip, has no effect on the charging and discharging of capacitor C3,

 

there is a possible explanation, to go back to the original chip manufacturers suggested RC circuit,as in first post,
there is nowhere near enough resistance or capacitance in the circuit to provide more than a very small fraction of a seconds delay,this might have been deemed enough.
dosent explain why there is quite a long delay on the LF chip though.
papabravo. cant wait to hear your thoughts on this point.....

 

as there are 2 speaker cabs the boards are duplicated, i am able to interchange them easily.
but its the the same on both output main amp boards..


might be worth changing the cap or resistor to a higher value.
also in the full schematic post 10 there is a paralel resistor presumably this would have
no effect on time, could it be to discharge the cap.

 

OK. So the small block labeled "MUTE/ST-BY" is actually inside another chi

yes it is fed from a circuit on the preamp board based on UPB3 which i think provides little in the way of a delay ,
but of course provides the mute voltage of rail minus zener.

 

I have looked at the datasheet and cannot discern any textual explanation for how the "MUTE/ST-BY" block might effect the charge discharge times based on the values of R5 and C3. In the "representative schematic" there are some transistors which may effect the charging and discharging currents based on threshold voltages which might have an effect, but I don't see how to quantify those effects.