Attached is a digital circuit of the MC14518B.

What's the real meaning of that combination in the red circle? Would it be like a buffer? I mean, the input is being inverted, then goes to another not gate with the bubble at the input. Would it be the same if I just put the normal gate symbol instead?

 

Attached is a digital circuit of the MC14518B.

What's the real meaning of that combination in the red circle? Would it be like a buffer? I mean, the input is being inverted, then goes to another not gate with the bubble at the input. Would it be the same if I just put the normal gate symbol instead?

Yes, the combination of the two inverters is to make a buffer. The two inversion circles cancel out. Logic diagram designers sometime like to move the inversion bubbles around as a way of tying the logic of the diagram more directly to the logic of the solution it is implementing.

You will see buffers drawn as two normal inverters in series or like as shown here. The idea here is to show the implementation while also emphasizing that it is just a buffer since both the input and the output of the two-gate combination are non-inverted.

You will also see it shown as just a single triangle gate with no bubble to emphasis only the high-level concept of the buffer, but if you were to drill down into it you would discover that it is still implemented as two inverters in series.

 

Yes, the combination of the two inverters is to make a buffer. The two inversion circles cancel out. Logic diagram designers sometime like to move the inversion bubbles around as a way of tying the logic of the diagram more directly to the logic of the solution it is implementing.

You will see buffers drawn as two normal inverters in series or like as shown here. The idea here is to show the implementation while also emphasizing that it is just a buffer since both the input and the output of the two-gate combination are non-inverted.

You will also see it shown as just a single triangle gate with no bubble to emphasis only the high-level concept of the buffer, but if you were to drill down into it you would discover that it is still implemented as two inverters in series.

Got it. Thank you.

So the purpose with two inverters is to make a kind of delay?

 

Attached is a digital circuit of the MC14518B.

What's the real meaning of that combination in the red circle? Would it be like a buffer? I mean, the input is being inverted, then goes to another not gate with the bubble at the input. Would it be the same if I just put the normal gate symbol instead?

What @WBahn said.

Additionally, the buffers on the outputs exist for most "B" series CD4000B CMOS logic. B means "buffered".

The buffer improves the rise/fall times of the output signals and makes them symmetrical, and reduces the output impedance.

This is a dramatic improvement over the original CD4000 series CMOS logic.

http://www.ti.com/lit/an/scha004/scha004.pdf

 

Got it. Thank you.

So the purpose with two inverters is to make a kind of delay?

Possibly, but more probably it is to buffer the signal for one (or both) of two reasons. First, to give it additional drive strength so that it can fan out either to more inputs or can drive long lines on the chip or the PCB. At the same time, the rise/fall times are normally better matched to the spec document. Second, to isolate the output of the FFs from the disturbances on other lines. Some FFs do not have buffered outputs (here I'm talking about FFs that are used on integrated circuits as opposed to commercially packaged FF chips). If the output of such a FF gets overdriven you can actually change the state of the FF. In fact, that is how you change the state of many on-chip FFs in order to achieve smaller, faster, lower-power designs.

 

So the purpose with two inverters is to make a kind of delay?

No; the added delay is an unwanted consequence. The requirement for that part of the circuit is a non-inverting buffer so problems at the output pin do not cause all of the internal circuits to function incorrectly. Unfortunately, the smallest most simple buffer is a single transistor, which inverts the logic polarity. Hence the 2nd inverter to re-right the logic.

ak

 

Internally all non-inverting logic blocks consist of two inverters in series.
That diagram just shows that for all the non-inverting buffering.

 

No; the added delay is an unwanted consequence.

It's USUALLY an unwanted consequence -- but sometimes it IS there for the delay. You see this a LOT in fundamental mode machines and asynchronous logic, typically as a means of dealing with critical races.

 

It's USUALLY an unwanted consequence -- but sometimes it IS there for the delay. You see this a LOT in fundamental mode machines and asynchronous logic, typically as a means of dealing with critical races.

There also are serpentine traces in PCI interfaces. But the question in post #1 is about the internal construction of a MC14518B.

ak