I wanted to understand the 74LS00 in terms of transistors, in order to figure out: why when the input pins aren't connected to anything they have a logic value of 1.
Searching online I wasn't able to find the actual circuit with the transistors that is used in each NAND gate in the IC.
I would appreciate it if someone could provide me with the transistor diagram of the 74LS00 in order to explain the no input counting as value 1.

Thank you in advance.

 

The basic structure of a TTL integrated circuit including the 7400, 74H00, 74LS00m and 74S00 is built around something that does not exist in the world of discrete transistors. That is the multi-emitter transistor. Imagine if you can a transistor with 2 emitters, one base, and one collector. Each of the emitters is connected to one of the inputs on a 2-input gate. As in a standard transistor, an emitter will source current if an external device is able to pull it low. For the LS series it should source approximately 400 μa which is also known as 1 standard LS load.

Check out the following article
https://www.elprocus.com/transistor-transistor-logic-ttl/#:~:text=TTL Comparison with Other Logic Families , Good 5 more rows

 

Welcome to AAC!



7400 circuit diagram

The base of Q1 is tied to Vcc via a 4kΩ resistor.
If no current flows through the base-emitter junction then the voltage at the base is Vcc or 5V.
Since there is no current through the base-emitter junction, the voltage at the emitter would also be at 5V.
However, there is leakage current through the diode connected from the emitter to ground. This current is very small. The voltage at the input would be sitting at some voltage lower than 5V and certainly nowhere close to 0V.

In order to pull the input (emitter) to GND you need to give it a path to GND, for example using a pull-down resistor.

What is the maximum value of this resistor that will present a logic LOW input?
To determine this you need to look up the datasheet.

Datasheet states IIL is -0.4mA at VI = 0.4V
This the current flowing out of the input to bring the input voltage to 0.4V.
Applying Ohm's Law:
R = 0.4 / 0.4mA = 1kΩ

To be on the safe side, make R a bit less than 1kΩ, for example 470-750Ω

Edit: Circuit diagram shown is for 7400 gate while the calculation is for 74LS00 gate.

 

When the input pins of any logic gate are open circuit, the output is undefined. It can be high or low, depending on the architecture, static charges and EMF radiation. There are lots of different circuits of nand gates online.

 

Thank you for the quick response.

If you can I have some follow-up questions:
1) Does "fan-out" describe the amount for transistors (or emitters in non discrete transistors) in a circuit.
2) I am still unsure about the floating inputs and how a transistor (specifically in the 74LS00) "reacts" to them.
3) I am not able to find a diagram for the NAND gate in the article you linked.

Thank you again for your answer, I hope these questions aren't too much of a hustle

 

See pdf attached.

 

I am not able to find a diagram for the NAND gate

It is circuit diagram of 74LS00 NAND gate:

 

Thank you for the info

I previously responded before the next few posts showed up.
I am struggling to understand the leakage current you mentioned and it's magnitude.

 

Thank you for the info

I previously responded before the next few posts showed up.
I am struggling to understand the leakage current you mentioned and it's magnitude.

If you look at the I-V (current vs. voltage) curve for a typical silicon diode you will see that when the diode is reversed biased, there is a very small (on the order of micro amperes) "leakage" current that flows. This is what happens to a diaode when the reverse bias is less than the breakdown voltage. When the maximum reverse bias is exceeded the diode will get hot, and like the Wicked Witch of the West, let out the "magic smoke" and melt.

 

Every P-N diode is governed by the Shockley diode equation.



The reverse bias saturation current is given by Is and varies from diode to diode.
The value of Is is extremely small, of the order of nano-amps.

Reference: https://en.wikipedia.org/wiki/Shockley_diode_equation

 

Thank you for the quick response.

If you can I have some follow-up questions:
1) Does "fan-out" describe the amount for transistors (or emitters in non discrete transistors) in a circuit.
2) I am still unsure about the floating inputs and how a transistor (specifically in the 74LS00) "reacts" to them.
3) I am not able to find a diagram for the NAND gate in the article you linked.

Thank you again for your answer, I hope these questions aren't too much of a hustle

1) "Fan out" describes how many logic inputs an output can safely drive.
2) Logic circuits are never designed with floating inputs because they can cause unpredictable behavior of the circuit. They are always tied high or low. Do not concern yourself with them because they are not a valid option.
3). https://www.google.com/search?q=nan...HXBoAUcQ_AUoAXoECAEQAw&biw=1280&bih=671&dpr=1

 

When the input pins of any logic gate are open circuit, the output is undefined.

Only for some logic families. For example, for TTL and ECL, the output is defined. The floating input stage is more susceptible to noise than a properly terminated input, but the result has been well documented since the 60's.

ak

 

See my models:

 

2) I am still unsure about the floating inputs and how a transistor (specifically in the 74LS00) "reacts" to them.

Specifically for TTL circuits, output current must be drawn from the input (connected to ground) to give a logic zero, and there is no significant input current if the input voltage is a logic high.
So if the input is open, there is no current flow, and that input is then seen as a logic one.

But if you want an input to be permanently logic high then it should be tied to the 5V supply through a resistor (e.g. 10kΩ), to eliminate any problem from noise.

 

Thanks for the responses.

I don't mean to stay on this topic forever, but from the diagram of the NAND gate I am still not sure how to interpret the current flow when the inputs are floating.

 

Thanks for the responses.

I don't mean to stay on this topic forever, but from the diagram of the NAND gate I am still not sure how to interpret the current flow when the inputs are floating.

Why do you feel that you need to? All you need to know is why you should never leave them floating.

 

You don't need to worry about current flow.

Drive the input from the output of another gate from the same logic family. This will guarantee that the logic LOW and HIGH levels are satisfied.

Otherwise, provide a pulldown or pullup resistor that will guarantee the required input voltages.
What you need to know are IIL @ VI and IIH @ VI given in the datasheet.

Never leave the input floating.

 

You don't need to worry about current flow.

Drive the input from the output of another gate from the same logic family. This will guarantee that the logic LOW and HIGH levels are satisfied.

Otherwise, provide a pulldown or pullup resistor that will guarantee the required input voltages.
What you need to know are IIL @ VI and IIH @ VI given in the datasheet.

Never leave the input floating.

It is much safer to pull a TTL input up. Using a pulldown with a modest value will cause the current from an input emitter to produce a voltage that may exceed the input low threshold. For example, if the input sources 400μa into a 2.2KΩ pulldown the there will be 880 mV across the resistor, putting the input voltage in the no man's land between 0.8V and 2.0V. TTL is NOT like CMOS in this regard. If you are going to use a pulldown make sure it is an appropriately low value. A standard TTL input which sources four times as much current will be even more unfogiving on the use of a pulldown resistor. For standard TTL I would not use a pulldown in excess of 470Ω.

 

All you need to know

Always a sign of a bad answer, especially as a response to this:

I wanted to understand

This thread is not about need, it is about knowledge.

The behavior of an 'LS00 floating input is relatively easy to explain with the schematic in post #7, as an updated version of older DTL devices.

To the TS: If you still need clarity on this, I can walk you through an LS gate input stage operation.

However, the same cannot be said for the '00 and 'S00 gates, whose schematics are in posts #3 and #6. As a public service, I'll quasi-hijack his question and shift it to those parts. For a standard, old, original 7400 NAND gate (or, to make things even more simple, a 7404 inverter) why does a floating input(s) cause a low output? Hint - is the main culprit base-collector leakage current, or something else?

ak

Representative schematic ( https://www.ti.com/lit/ds/symlink/sn7404.pdf )

 

I am still not sure how to interpret the current flow when the inputs are floating.

Note that the inputs are the emitter of an NPN transistor, so current needs to flow in the direction of the arrow (out of the emitter to ground) to turn on the transistor and pull its collector low, which causes the transistor connected to its collector to also be off..
When the input is open, there is no place for the emitter current to flow, so the transistor is off.
This causes current to go from the 4k resistor through the the now forward biased collector-base junction, turning on the second transistor.
Make sense?