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Would it harm a CD4081 to force its output briefly high (1us)?
Would the answer be different for a CD4081B?
VDD = 5V
Would the answer be different for a CD4081B?
VDD = 5V
Pull CD4081 output briefly high, damage the chip?
- Thread starter AlbertHall
- Start date
How high?
That will cause a current spike through the substrate which could cause damage if high enough.
A resistor in series with the output would minimize that.
Generally not. You will notice that the data sheet doesn't show an "absolute maximum" figures for output current. The MOSFETs have such a high Rds(on) that they limit the current to a safe amount.
If you take the inputs or outputs above the positive supply or below the negative supply you might not be so lucky.
The output stage of a CD4000 series part consists of a complementary pair of MOSFETS. There are two possible states: HIGH or LOW. If the output is in the HIGH state, then applying a high signal will have minimal effect. If the output is in the LOW state, then applying a HIGH signal is the equivalent of providing a dead short from VDD (3V-18V) to GND. This can be quite damaging. You would be well advised to find an alternate solution.
You could use an OR gate to combine the output of the CD4081(B) with the 1us pulse. This would be the safe and rational thing to do. I understand there may be impediments to this solution. If that is the case, you may be SOL.
I would only be pulling it up to the chip VDD.
If the output is low when you do that, it will still be a short across the VDD power supply. If you want to do the experiment, try it on a breadboard and measure it. You could also try it in a simulator.
OK, I'll take the hint and come up with another way of doing it.
Yes, but...
This an existing board with quite dense tracks so adding this resistor would involve tracing the tracks to find a place where I could cut the track and solder an SMD across the ends and I would need to do this in five places (it would also need 5 diodes).
How often does this 1us short occur?
look at the graph in the data sheet:
At 5V drain to source the current is going to be 4mA, that’s 20mW dissipation, for one microsecond, and it can dissipate 500mW indefinitely. It’s not going to come to any harm, even if it repeats every 2 microseconds, and even if you subject all four gates in the package to the same thing.
. . .but I never said is was such a great design technique, and don’t try it with HCMOS!
look at the graph in the data sheet:
At 5V drain to source the current is going to be 4mA, that’s 20mW dissipation, for one microsecond, and it can dissipate 500mW indefinitely. It’s not going to come to any harm, even if it repeats every 2 microseconds, and even if you subject all four gates in the package to the same thing.. . .but I never said is was such a great design technique, and don’t try it with HCMOS!
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The short would be perhaps once per day but I have come up with an alternative which avoids cutting tracks and cruelty to MOSFETs. The final result isn't quite as 'pretty' but it is a lot easier and will do the job.
Could you briefly describe it?
It will survive. The cross conduction of a 555 changing state is far worse!
Three of the gates in the CD4081 operate the resets on a counter chain.
I will now send many pulses very fast and wait for the overflow from the final counter in the chain to know that the count is back to zero.
