I am trying to simulate a three-stage opamp circuit consisting of a differential amplifier as its first stage, a CSA as its second stage and a Source FOllower as its third stage. My .op and .tran simulations are working fine. But I am having a problem with AC simulation. An error comes up saying:
Questionable use of curly braces in ".model sir870adp vdmos(rg=3 vto=2.9 rd=3.2m rs=1.5m rb={m} kp=100 mtriode=1.85 cgdmax=1.4n cgdmin=70p cgs=2.9n cjo=3.6n m=.4 a=.7 vj=.7 lambda=20m is=3p ksubthres=.08 mfg=siliconix vds=100 ron=5.5m qg=53.5n)"
Error: undefined symbol in: "[m]"
Instance "m10": Length shorter than recommended for a level 1 MOSFET.
Instance "m10": Width narrower than recommended for a level 1 MOSFET.
I am attaching the LTSpice schematic and the model file which I am using (tsmc180nmcmos.lib). Please have a look and tell me what is going wrong.
Questionable use of curly braces in ".model sir870adp vdmos(rg=3 vto=2.9 rd=3.2m rs=1.5m rb={m} kp=100 mtriode=1.85 cgdmax=1.4n cgdmin=70p cgs=2.9n cjo=3.6n m=.4 a=.7 vj=.7 lambda=20m is=3p ksubthres=.08 mfg=siliconix vds=100 ron=5.5m qg=53.5n)"
Error: undefined symbol in: "[m]"
Instance "m10": Length shorter than recommended for a level 1 MOSFET.
Instance "m10": Width narrower than recommended for a level 1 MOSFET.
I am attaching the LTSpice schematic and the model file which I am using (tsmc180nmcmos.lib). Please have a look and tell me what is going wrong.
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