Hi all,
I am attempting to write a routine using MPLABx and XC8 for the PIC12F629 where timer0 overflows approximately every 50mS. To do this, I have assigned the prescaler to the TMR0 and made its value 1:256. My math & thought process is:
0.05 seconds / (instruction time)
0.05 / (0.000001) = 50000
50000 / 256 (prescaler) = ~195 instruction cycles
256 - 195 = 61
So, by preloading TMR0 with 61, I should achieve overflow after 195 cycles (after the prescaler of course).
My code for this bit:
Now, I understand that writing to Timer 0 skips some instruction cycles, so I am attempting to look at disassembly to determine how many instruction cycles it takes to preload the timer0 register so that I can adjust the preloaded value to account for this, and maintain as close to 50mS overflow time as possible. When I look at the disassembly of the ISR, I am unsure of what is happening between ADDWF TMR0, F and the RETFIE instruction. Can someone help me understand what is happening here?
Disassembly:
I am attempting to write a routine using MPLABx and XC8 for the PIC12F629 where timer0 overflows approximately every 50mS. To do this, I have assigned the prescaler to the TMR0 and made its value 1:256. My math & thought process is:
0.05 seconds / (instruction time)
0.05 / (0.000001) = 50000
50000 / 256 (prescaler) = ~195 instruction cycles
256 - 195 = 61
So, by preloading TMR0 with 61, I should achieve overflow after 195 cycles (after the prescaler of course).
My code for this bit:
Code:
void interrupt isr(void)
{
request = TRUE; //SET REQUEST FLAG
TMR0IF = 0; //CLEAR TMR0 INTERRUPT FLAG
TMR0 += 61; //PRELOAD TIMER 0
}
Disassembly:
Code:
! TMR0 += 61; //PRELOAD TIMER 0
0x2B: MOVLW 0x3D
0x2C: MOVWF __pcstackBANK0
0x2D: MOVF __pcstackBANK0, W
0x2E: ADDWF TMR0, F
!}
0x2F: MOVF 0x24, W
0x30: MOVWF 0x5F
0x31: MOVF 0x23, W
0x32: MOVWF PCLATH
0x33: MOVF 0x22, W
0x34: MOVWF FSR
0x35: SWAPF 0x21, W
0x36: MOVWF STATUS
0x37: SWAPF 0x5E, F
0x38: SWAPF 0x5E, W
0x39: RETFIE
Last edited: