Hi,

I see a lot of decoupling capcitors connected in parallel on power rails . I would like to know why they choose to do this? Why not have 1 capacitor instead? How does it help?

 

Stupid way to draw a schematic. The capacitors are really installed next to the ICs to insure steady voltage at the chip.

See also: http://forum.allaboutcircuits.com/threads/decoupling-or-bypass-capacitors-why.45583/

 

It is a common drafting practice to put all the decoupling caps on one page of a schematic. This practice uncomplicates the schematics that contain the heart of the design.

 

uncomplicates

Uncomplicates the schematic until you find 8 decoupling capacitors and 9 chips.

I guess we're suffering from a difference of opinion here.

 

There could be 9 chips (op-amps) and 18 (plus) decoupling caps.

 

Anyway, engineers like to see the decoupling caps near the chips they are decoupling/protecting and the drafters don't care where the caps are on the schematic.

 

Oh.my.Dog. That was my post #13,000!

Anyway, my point is that when the counts don't match I have to try to figure out where the caps really are. If I am repairing the board, I can see the caps. If I only have the schematic, I end up wondering a bit. So, yeah, my mind is more toward the engineering side. I am a bit of a draftsman, but I would make an effort to indicate where the caps are physically located. Point of annoyance: Many chips have the Vcc and Vee on opposite corners of the chip. When you're drawing the circuit, you can just put the pin labels where it's convenient. When you get to the board, the caps would be so much more convenient to place if both power pins were on one end of the chip.

 

That makes sense. Thanks a lot for the help Glad to ask the question that had your post number 13000!!

 

Hi,

I see a lot of decoupling capcitors connected in parallel on power rails . I would like to know why they choose to do this? Why not have 1 capacitor instead? How does it help?


View attachment 92477

There are other reasons for paralleling caps, besides the bad schematic-drafting practices already mentioned: You can sometimes get better performance by paralleling more smaller caps than by using one large one. It depends on what you are doing, and on the properties of the caps. For example, you might get a lower effective ESR (Equivalent Series Resistance) by paralleling, than you would with one larger cap. Or maybe you could need multiple caps at different distances from a device, to get a spread of trace inductances, or even to parallel the trace inductances to attempt to reduce the effective inductance. It could also sometimes be cheaper to use multiple smaller caps than using one larger one. And sometimes redundancy might be a good thing, too.

 

In actual practice we used different values in parallel, typically 103 (.01 μF), 104 (.1 μF), and 105 (1 μF). The lower values attenuate high frequency noise and the larger ones supply current to the nearby chips. CMOS at high frequencies can be as bad or worse than original TTL.

 

I agree that each individual small capacitor will go where it's needed. However, I'd stop short of saying that it's bad schematic practice to draw them like that. When I worked for a major computer manufacturer, we might draw in bypass capacitors for a processor, or something that we knew would be high current (like the switch for a power supply), and in those cases, would annotate that they should go as close as possible to such-and-such component, or in the case of Intel processors, there was even a fixed bypassing layout that we didn't deviate from. But all the other bypass caps were left to PCB layout people, who dropped them in on the fly during layout. The caps were then back-annotated into the schematic, and all appeared on one page. It would have been too much trouble for the layout people to locate the exact page on the schematic, and put the cap there (time to market was paramount in that business).

 

in those cases, would annotate that they should go as close as possible to such-and-such component,

The difficulty that brought Rock_Slate here is that his schematic was NOT annotated, and that is what I'm calling, "bad". There are plenty of schematics that only show a row of small caps with no instructions about where they are physically located.

(time to market was paramount in that business).

It would seem that, "time to market" can be so paramount for some manufacturers that they don't take the time to annotate at all.

 

Like most things, adherence to "best practices" (even assuming that we could actually agree what those were to begin with) is highly variable. In many cases, it strongly depends on whether the item in question is at the heart of the company's business, or is somewhat peripheral to it. A company that does electronic design day in and day out and has had the opportunity to feel the pain caused by poor documentation tends to be better at documentation than a company is that does occasional such designs and seldom gets bit, for whatever reason, by their documentation shortcomings.

 

I am going to have to disagree with a few people here. When you have a 21 layer board with every square centimeter populated, there will be 20 to 30 pages of schematics for it. I learned to appreciate that drafting put the decoupling caps on one or two pages. I also appreciate when they put the I/O connectors on separate pages. So, what am I saying? A four layer board with 40 components is one thing, a 21 layer board with 800 components is another. When the board is HUGE you have to make concessions to keep it simple otherwise the schematics become unreadable.

 

I am going to have to disagree with a few people here. When you have a 21 layer board with every square centimeter populated, there will be 20 to 30 pages of schematics for it. I learned to appreciate that drafting put the decoupling caps on one or two pages. I also appreciate when they put the I/O connectors on separate pages. So, what am I saying? A four layer board with 40 components is one thing, a 21 layer board with 800 components is another. When the board is HUGE you have to make concessions to keep it simple otherwise the schematics become unreadable.

This is where I think I really benefited from doing IC design before I did large board design. On an IC, you do NOT try to put everything on one page or to make it flat in any way shape or form. Not when there are tens of thousands of transistors on even a tiny IC and many millions on a large one. You make your design very hierarchical and your top level design consists of your I/O pads. Even these tend to be in the form of several functional blocks because an IC might have several hundred I/O pins.

So when I designed test boards (one of which had over 3000 solder pads on it) I used the same approach and had board schematics that where hierarchically organized and everything went beautifully. But this is something that I seldom see in other board designs where the norm seems to be basically one huge schematic that is simply spread out over many pages. I generally find those very hard to navigate.