I was searching and reading about power integrity importance for FPGA/SOC based PCBs. Some important points in this regards are:

1- Use thinner dielectric between power and ground plane.
2- Use multiple de-coupling capacitors in parallel for example 1uF, 100nF, and 10nF.
3- Use smaller packages for example 0603 and 0402 and mount them close to the IC.

I am thinking about the dielectric material and dielectric constant. We know that this is important in signal integrity to use low loss material with lower dielectric constant. How the dielectric constant is influenced on the power integrity ?

 

The IoT trend is expected to rise exponentially. The compliance in the RF category is already challenged to keep up.
A material science/EE approach means robotics. What has been aerospace materials will be need to become cost effective
and RF pcb manufacturing will need to innovate at a brisk pace to find new ways to structure composite ceramic based
boards away from flat layers into 3 dimensional conductive channeling. The Design software being a limiting factor.
Tantalum capacitors help absorb transients and more absorbing is needed around outer circumference laden with io pins.
In addressing crosstalk with the latest microcontrollers a ceramic based/FR4 composite means changes in production methods.