Hi,
I am going to be interfacing to a FLASH device from a processor on power up to obtain boot up information. After this is done, the requirement is to not being allowed to access this FLASH device unless another power on cycle occurs.
The interface to the FLASH will be done by using the processors QSPI interface. The processor also has GPIO signals as well.
On power up these GPIO signals are in a high-z state until after the processor has booted from FLASH and configured these signals.
My plan is to do the following. Looks for some feedback on whether this approach makes the most sense.
Please see attached block diagram
Thanks!
I am going to be interfacing to a FLASH device from a processor on power up to obtain boot up information. After this is done, the requirement is to not being allowed to access this FLASH device unless another power on cycle occurs.
The interface to the FLASH will be done by using the processors QSPI interface. The processor also has GPIO signals as well.
On power up these GPIO signals are in a high-z state until after the processor has booted from FLASH and configured these signals.
My plan is to do the following. Looks for some feedback on whether this approach makes the most sense.
Please see attached block diagram
Thanks!
