PMOS current mirror - Small signal analysis - Why is Vsg = 0v?

The one in red box , why is Vsg2 = 0V?
Vsg2 = Vs - Vg --> Vs = 0 since it is ground but what about vg?

 

As the red writing by the red box says, it is at a fixed DC voltage and there can be no AC voltage there so it acts for AC signals the same as ground or Vdd.

 

Actually I still don't get it
I am trying to do a circuit analysis on the red box but I am not sure why it is 0 V for Vsg2
Vs=0 V since it is grounded but Vg isnt equal to Vout?
So Vs-Vg = Vsg2 --> Vsg = 0 - Vout???

Did I do it wrongly for analysis part?

 

You are thinking DC, but the red box is considering AC. There is zero signal voltage on the gate of the top FET.

 

No the M2 gate is connected to M3 not the the output.
http://forum.allaboutcircuits.com/threads/ac-analysis-of-a-ce-amplifier.127252/#post-1037659

 

Saying vsg2 = 0 means 2 things:
1) M3 and IREF can be replaced by a DC voltage source from source to gate of M2.
2) DC voltage sources are shorted for small-signal analysis.
Therefore, vsg2 = 0