pll freq synthesis

danadak

Joined Mar 10, 2018
3,770
You can use a programmable divider in feedback loop to
produce x N synthesizer. Page 19 of previous attachment doc.

Regards, Dana.
 

danadak

Joined Mar 10, 2018
3,770
For sure. There was another gent, can't remember, who did extensive analysis
on non linear behavior, more accurate lock calculations, S/N....but book cost
more than my net worth. Maybe at the pearly gates I will get a peek if I am
good....damn, too late for that :)

Regards, Dana.
 

ericgibbs

Joined Jan 29, 2010
9,297
hi 48,
The clip that have posted is for the Lowest Maximum frequency.
eg: at 15Vdd typical Fmax = 2.7MHz, but a device may only have a Fmax =1.3MHz as a worst case.
E
Note: there always a spread in a performance parameter about the stated Typical value.
 
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