Hi all,

i have a question about a PLL (phase locked loop).

Is it possible that the filter (in my case an integrator) require more iterations if the signal strength is lower?

Does the signal strength have an influence on the PLL, because that’s what I observe?

Regards,

JS

 

If you look at classic approximations used to calculate lock time
you will see they are independent of amplitude. It goes to the
fact you are trying to make a phase measurement, which assumes
amplitude is satisfactory to do this.

Google "weak signal detection pll", lots of hits.

Regards, Dana.

 

Then again there are analog phase detectors in which the loop gain is a function of amplitude, and in that case pull-in time can be affected by the amplitude.

 

Thank you

 

Then again there are analog phase detectors in which the loop gain is a function of amplitude, and in that case pull-in time can be affected by the amplitude.

View attachment 151756

@DickCappels

do you mean the gain of the phase detector KD?

Regards,
JS

 

yes

 

and the last question...

Is it also possible that the phase of the signal has an influce on the integrator of the PLL ?

Regards,
JS

 

and the last question...

Is it also possible that the phase of the signal has an influce on the integrator of the PLL ?

Regards,
JS

Trying to understand, influence in what way?

 

I think it is easier if I explain the problem.

I am using the integrator of the PLL to obtain the difference between the internal clock frequency and the frequency of the external signal. This difference is used to correct the time measurements for the localization. (Because one clock is faster or slower)

Now I have observed that this integrator is effected by the length of the cable.
Unfortunately, I cannot reproduce this difference if I increase the gain of my signal in the same manner as the cable reduce the gain.
It looks like that the gain has an effect but not that high.

Therefore, I am thinking that it is maybe due to the phase change.

Regards,

JS

 

What kind of phase comparator are you using?
What kind of signal is coming down the cable (sine wave, bipolar square wave, rectangular pulses...)
If you post schematics showing the PLL and its filter that would help a lot.

 

Unfortunately, I don’t know which comparator is used.
It is a Decawave chip for UWB (ultra wideband) position estimation, but I will ask them if they can provide me the schematics.
But do you think that it is possible that the integrator require more iteration if the phase (length of the cable) changes?

(PS.: Thank you very much for helping me to find the answer)

Regards,

JS

 

Are you using the DW1000?
Is the signal that is coming over the cable EXTCLK (38.4 MHz)? This is more or less a digital input. Changing the cable length wold cause a shift in phase between the clock source and the chip (phase being another term for relative time), but I do not see how that would affect the RF PLL if you are using the chip the same was as in the application circuit (Figure 37) in the datasheet.

Is the integrator an active circuit (includes and amplifier) or is it the RC network attached to VCOTUNE?

What is the nature of the problem, are you unable to lock in on the incoming signal?

What does your clock input circuit look like? Is the clock signal terminated properly -mistermination or lack of termination can cause the signal to become too small for the chip to "see" and this would be a function of cable length.

Still trying to get a picture of what you have.


What are you using as an input to the integrator?

If you are using this to locate a "remote" transmitter then the PLL used for communications should be locking onto the transmitted signal.

Edit: It does not seem reasonable that changing the cable length would affect the integrator provided you are using the chip in the conventiona manner.

 

Are you using the DW1000?
Is the signal that is coming over the cable EXTCLK (38.4 MHz)? This is more or less a digital input. Changing the cable length wold cause a shift in phase between the clock source and the chip (phase being another term for relative time), but I do not see how that would affect the RF PLL if you are using the chip the same was as in the application circuit (Figure 37) in the datasheet.
.

Hi,

Yes I am using DW100 with the EVK1000 Evaluation Kit.

No sry you misunderstood me. Instead the antenna I am using a cable to transmit the data. So it is the signal coming from another EVK1000 device.

The receive carrier integrator reflects the frequency offset of the remote transmitter with respect to the local receive clock. A positive carrier integrator value means that the local receive clock is running faster than that of the remote transmitter device.

If I change the cable length the integrator of PLL changes. Therefore, I assumed that with changing phase of the carrier the phase detector require more or less iterations.
The power of the signal effects the integrator as well but not that much as the change of the cable length.



In the pictures you can find the used PLL filter.

 

I have a poor understanding of the chip, but is it the case that when two chips are in communication with each other one is measuring the time for a round trip of the signal. Is that correct? If so, it is only measuring the length of the cable.

Edit: You said that when you change the cable length the integrator chances. Do you mean the voltage on the output of the integrator

Edit: Which integrator (which pin)?

 

Yes you are correct. It is measuring the length or the cable. The pll is inside of the dw1000 ic and the integrator value can be read from the register. With the integrator value (in ppm) it is possible to correct the flight time.

If the length of the cable is changed the value of the integrator in ppm is changed as well. And at this point I don’t know why.