first thank you for trying to help me, I am new in studding electronics the problem is I tried to read the data sheet but there are some things I can't understand P0 to P3 are Parallel Inputs what is the meaning of parallel input in decade counter and how can I use them secondly what is CEP and CET and what are they use for and what is TC

 

From datasheet:
CEP - count-enable P
CET - count-enable T
They both need to be set to High (2-5 volts) to start the count.

The inputs ABCD is to load the starting value. I guess if you connect them to ground (Low), then you load a starting value of 0000. If I read datasheet right, the '160 is BCD counter. So the counter goes:
0000
0001
0010
-
-
-
1001
You start at 0, you end at 9.

 

From datasheet:
CEP - count-enable P
CET - count-enable T
They both need to be set to High (2-5 volts) to start the count.

The inputs ABCD is to load the starting value. I guess if you connect them to ground (Low), then you load a starting value of 0000. If I read datasheet right, the '160 is BCD counter. So the counter goes:
0000
0001
0010
-
-
-
1001
You start at 0, you end at 9.

thank you sir but I wanna know what will happen if i connect CET and CEP once active low and once active high what will happen

 

thank you sir but I wanna know what will happen if i connect CET and CEP once active low and once active high what will happen

Nothing.
The count starts when they are both High. If they are both Low, the count is off. If one is High, the other is Low, the count is off.

 

If you look at the logic diagram of '160, you will see that CEP and CET are connected to AND gate. Do you know truth table for an AND gate?

The output of an AND gate is High only when inputs are High.

So when you send CEP Low and CET High, the output of the AND gate is Low. When you send CEP High and CET Low, the output of the AND gate is Low.

 

If you look at the logic diagram of '160, you will see that CEP and CET are connected to AND gate. Do you know truth table for an AND gate?

The output of an AND gate is High only when inputs are High.

So when you send CEP Low and CET High, the output of the AND gate is Low. When you send CEP High and CET Low, the output of the AND gate is Low.

sir I see the logic diagram and I fond CEP and CET are conected to NAND gate but the output where it is going to in the attached image

 

sir I see the logic diagram and I fond CEP and CET are conected to NAND gate but the output where it is going to in the attached image

I was looking at this one: http://www.ti.com/lit/ds/symlink/sn74160.pdf

 

sir can you help me to understand what highlighted

 

this is what i highlighted

 

this is what i highlighted

The count is paused.
All the cases are listed in the Mode Select Table.

 

I was looking at this one: http://www.ti.com/lit/ds/symlink/sn74160.pdf

sir can you help me to understand what highlighted