Hey everyone,
So a project i've been working on has been working great in the lab, but once i moved into the real world where cables were longer and such there was alot of interference, so i changed a bunch of stuff to communicate using differential pairs rather than sending a single signal over a cable. Unfortunately now I either need to add cables or find a way to power the board using the same cables as the UART signals. My thought was simply to drive the signal from the master device at higher power (8v and GND) using a mosfet or optocouple off the microprocessor, and at the remote daughter board treat it like AC current and rectify it and store some energy into a cap while also using a voltage divider to bring the signal down to logic levels.
View attachment 165548
*EDIT: I did forget to put resistors on the optocouplers in this schematic, and if the general premise of the schematic will work i will likely change the transmits to use a D-Latch to ensure sync with clock.
My other idea to tackle this was to send 5v0 across a pair while treating 5v0 as logic low and use a charge pump to push the voltage higher to say 12v0 for logic high, but not sure how I would handle the differential pair for this while also having a ground connection.
I have quickly diagrammed the first idea.
Thanks very much guys, y'all have been a great help in my projects so far! Also just got my first FPGA developer board to mess around with(based on a Xilinx spartan 6)
So a project i've been working on has been working great in the lab, but once i moved into the real world where cables were longer and such there was alot of interference, so i changed a bunch of stuff to communicate using differential pairs rather than sending a single signal over a cable. Unfortunately now I either need to add cables or find a way to power the board using the same cables as the UART signals. My thought was simply to drive the signal from the master device at higher power (8v and GND) using a mosfet or optocouple off the microprocessor, and at the remote daughter board treat it like AC current and rectify it and store some energy into a cap while also using a voltage divider to bring the signal down to logic levels.
View attachment 165548
*EDIT: I did forget to put resistors on the optocouplers in this schematic, and if the general premise of the schematic will work i will likely change the transmits to use a D-Latch to ensure sync with clock.
My other idea to tackle this was to send 5v0 across a pair while treating 5v0 as logic low and use a charge pump to push the voltage higher to say 12v0 for logic high, but not sure how I would handle the differential pair for this while also having a ground connection.
I have quickly diagrammed the first idea.
Thanks very much guys, y'all have been a great help in my projects so far! Also just got my first FPGA developer board to mess around with(based on a Xilinx spartan 6)
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