Hi all,
I read the following ,
"First of all, the 100MHz you refer to is the reference clock frequency. The reference clock is either shared between the motherboard and devices, or created from a local oscillator. This is not part of the throughput calculation.
To get the transceiver clock frequencies (the frequency of the high speed TX and RX lines), a Phase-locked loop (PLL) device is used to step this up the reference clock frequency to a higher value. The clock rates are 1.25GHz (2.5 Giga-transfers per second (GTps)) for PCIe Gen 1, 2.5GHz (5GTps) for PCIe Gen 2, or 4GHz (8GTps) for PCIe Gen 3."
Can you tell me why the clock is not doubled in gen3? And how is the clock speed decided to 4GHz? Is there any calculation? Please explain
Thanks
I read the following ,
"First of all, the 100MHz you refer to is the reference clock frequency. The reference clock is either shared between the motherboard and devices, or created from a local oscillator. This is not part of the throughput calculation.
To get the transceiver clock frequencies (the frequency of the high speed TX and RX lines), a Phase-locked loop (PLL) device is used to step this up the reference clock frequency to a higher value. The clock rates are 1.25GHz (2.5 Giga-transfers per second (GTps)) for PCIe Gen 1, 2.5GHz (5GTps) for PCIe Gen 2, or 4GHz (8GTps) for PCIe Gen 3."
Can you tell me why the clock is not doubled in gen3? And how is the clock speed decided to 4GHz? Is there any calculation? Please explain
Thanks