Parallel in serial out shift register question

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Werapon Pat

Joined Jan 14, 2018
35
I have one question about this. when we store data into D flip-flop, the data will not shift until the SH/(LD)' is activated right?


 

WBahn

Joined Mar 31, 2012
24,854
I have one question about this. when we store data into D flip-flop, the data will not shift until the SH/(LD)' is activated right?


One thing to note with that circuit is that it either loads new data or shifts current data on each clock cycle. Sometimes you want to load several shift registers from the same data bus before you start shifting all of them and thus you want them to NOT load any new data but also NOT shift current data. This circuit can't do that.

Can you see a way to modify it so that you have another input, SE (shift enable) so that when SH is HI but SE is LO that the current data simply stays put? (You can also make it /SE, active-LO, if that makes the implementation easier).
 

olphart

Joined Sep 22, 2012
78
Agreed, ya can't be silly at it, taking it out of sync invites race conditions and unpredictable stuff (BTDT).
At blush, maybe a F/F clocked on the opposite edge of the S/R to enable it.
Also gotta be careful not to cause a clock edge on enable / disable (BTDT-2).
 
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