I have one question about this. when we store data into D flip-flop, the data will not shift until the SH/(LD)' is activated right?
One thing to note with that circuit is that it either loads new data or shifts current data on each clock cycle. Sometimes you want to load several shift registers from the same data bus before you start shifting all of them and thus you want them to NOT load any new data but also NOT shift current data. This circuit can't do that.I have one question about this. when we store data into D flip-flop, the data will not shift until the SH/(LD)' is activated right?
If you are responding to my post above, then that is one option, but generally not the best. Gated clocks mean you are in the world of asynchronous logic and few people design such circuits correctly.Gate the clock...
by Aaron Carman
by Aaron Carman