Hi!
I was studying the propagation time of inverter CMOS. The text where I study considers only the gate capacitors and the drain capacitors of the NMOS and PMOS. This is schema:

The objective is calculate CL capacitors. The text says that the CL is in parallel with CDB,n ok because V3 = V2 = Vout - 0. Very well. Then it says that CDW,p is in parallel with CL. Why ?? For me V1 = Vdd-Vout and V3 = Vout - 0. Vdd = 1V. I don't understand because the CL is in parallel with CDW,p. Help me please.

 

From an AC standpoint, all three capacitors are in parallel.

To see how this makes sense, imagine that the output is currently LO and then the input changes to make it HI.

If there were just a single capacitor, C1, tied to ground, the total charge that would have to be provided by the PFET in order to charge this cap is C1·Vdd.

If there were just a single capacitor, C2, tied to Vdd, the total charge that would have to be provided by the PFET in order to discharge this cap is C2·Vdd.

So if both caps were present, the total charge provided by the PFET would be the sum of these two, which would be (C1+C2)·Vdd, which is the same as if a single capacitor equal to the sum of the two was connected to the output. That's the same as the two capacitors in parallel.