I'm trying to simulate a standard undervoltage lockout circuit in LTSpice, which should trip around 7 volts. Attached below is the circuit I modelled.

At 12 Volts, the negative end of U1 is greater than the positive end, so there should be 0 volts from the output and 0 volts at the gate. At around 7 volts, the positive end is higher than the negative end, meaning there's around 7 volts at the gate and V(gs) is around 0. I expect 0 volts at the drain of the MOSFET, but looking at the graph below there is still voltage at the drain.
(Green line is voltage at the drain, Blue is voltage at the gate)

I'd appreciate any help in resolving this issue.

 

It is very hard to understand what is going on in your simulation:

1. Choosing a black background and a trace color (dark blue) with no contrast is a very poor choice.
2. Showing us a picture is not all that helpful. Including the .asc file alone with any unique symbols and libraries so we can run the simulation and see what you are seeing would be superior.
3. None of the nets in your simulation have net names and V(n002) is not a helpful label. Give them names.
4. the resistors seem far larger than necessary for proper functioning of the circuit.
5. The operation of a P-channel FET requires the Vgs be negative WITH RESPECT TO THE source. How does your circuit, where the source is connected to V1 allow for this condition to be maintained before you get to the cutoff threshold?

 

Post your .asc file.

You need to add a resistive load to ground at the MOSFET drain.
If it is floating, you are seeing the leakage from source to drain.

 

I think this is functionally what you are trying to do. Is that correct?


I have used a behavioral voltage source to control the MOSFET gate

1. The gate is held at ground as long as V(Vi) > +7V. This implies that Vgs < -7V, and the MOSFET will be ON
2. The gate is held at V(Vi) when V(Vi) < +7V. This implies that V(G) should be the same as V(Vi), making Vgs = 0, and the MOSFET will be OFF.

ETA: This suggests the use of a garden variety open collector comparator. Is there some reason why you are using an opamp for this purpose?

 

Post your .asc file

Sorry for not Including it earlier, here it is.

 

I think this is functionally what you are trying to do. Is that correct?

View attachment 286909
I have used a behavioral voltage source to control the MOSFET gate

1. The gate is held at ground as long as V(Vi) > +7V. This implies that Vgs < -7V, and the MOSFET will be ON
2. The gate is held at V(Vi) when V(Vi) < +7V. This implies that V(G) should be the same as V(Vi), making Vgs = 0, and the MOSFET will be OFF.

Yeah, thats basically what I was expecting from the circuit. I followed this document when I was designing this circuit. I chose those values for the resistors since I wanted to minimize current drain as well as considering what I had available to me.

 

It seems that after adding a load to the output and doing the analysis again, it was working as intended. I'm going to be a bit more thorough for my next project. Thanks for your help everyone.

 

It seems that after adding a load to the output and doing the analysis again, it was working as intended. I'm going to be a bit more thorough for my next project. Thanks for your help everyone.

Of course, you know most real parts like the LT1495 and the LT1389 won't work down to 0V. Check the datasheet for actual supply voltage minimums.

 

It seems that after adding a load to the output and doing the analysis again, it was working as intended. I'm going to be a bit more thorough for my next project. Thanks for your help everyone.

A basic rule is to never leave any circuit nodes floating, or you will often get flaky results, both in a simulation or the real circuit.

For example, measuring the MOSFET output in a real circuit with a meter or oscilloscope would add their load to shunt the leakage current to ground.