Can anyone elaborate on why certain type of op-amp inputs exhibit output phase inversion when the input common mode range is violated? Many sources state that this is common with JFET amplifiers, sometimes BJT's and then MOS.
This is as far as the explanation goes. I know what phase reversal is, and I know how to test for it and prevent it.
What I do want to know is why JFETs (and BJTs) inputs are more likely to cause this.

 

It happens because one of the transistors in the input differential pair saturates. In the BJT, the collector-base junction becomes forward biased, so the voltage on the base shows up on the collector non-inverted, instead of inverted as is normal. In the JFET, essentially the same thing happens. The gate-drain diode is forward biased, allowing the signal on the gate to appear on the drain, noninverted.

 

Thanks Ron. I am going to take this as a jumping point and scare up some more research.

 

You can also get phase reversal by driving the input too high near the rails in some opamps, like the TL074N.

 

You can also get phase reversal by driving the input too high near the rails in some opamps, like the TL074N.

Are you sure TL074 reverses phase when you exceed the positive CM limit? I believe it's only when you exceed the negative limit, but I haven't tested hardware. Simulation shows it only on the negative peaks, but simulation can be wrong.

 

The inputs of a TL07x and TL08x work fine as high as the positive supply but phase reversal occurs if one input gets lower than a few volts above the negative supply voltage.
The input voltages must never exceed the supply voltages.