LTSpice
Simulation of integrator with reset-to-zero circuit for 2 Vin ramps (-V to +V and viceversa). The "chopping" signal (Vctrl) is used to verify the output at different ranges of Vin.
For Vin values above 0V, the output gets hard limited (?!). The reason obviously resides on the MOSFET whose source sits on the summing point (always at 0V). A sanity check shows the integrator itself, (no reset circuit), working OK.
For anyone interested I attached the .asc file plus the subckt file for the NMOS 2N7000 (also used the BS170 with similar results). I stripped out any .INCLUDE or .LIB directive since I am using now full paths to my bag of models and can forget copying models / subckts here and there every time.
Simulation of integrator with reset-to-zero circuit for 2 Vin ramps (-V to +V and viceversa). The "chopping" signal (Vctrl) is used to verify the output at different ranges of Vin.
For Vin values above 0V, the output gets hard limited (?!). The reason obviously resides on the MOSFET whose source sits on the summing point (always at 0V). A sanity check shows the integrator itself, (no reset circuit), working OK.
For anyone interested I attached the .asc file plus the subckt file for the NMOS 2N7000 (also used the BS170 with similar results). I stripped out any .INCLUDE or .LIB directive since I am using now full paths to my bag of models and can forget copying models / subckts here and there every time.
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