How to find offset voltage of the comparator of SAR ADC in LTSpice? Any suggestions? Its very important

 

Comparator offset is primarily a product of the device mismatch associated with the differential pair of transistors at the input of the comparator.

That said, do you have any transistor matching data for the semiconductor process that the comparator is on? The mismatch data can be inserted in a simulation as an ideal element.

If the comparator is a chip you are buying, then the spec sheet will have that information.

Rule of thumb - bipolar comparators will generally have input referred mismatch of 1-3 mV (some even less) A CMOS comparator will be worse, and is heavily dependent on the size of the transistors used.

 

Comparator offset is primarily a product of the device mismatch associated with the differential pair of transistors at the input of the comparator.

That said, do you have any transistor matching data for the semiconductor process that the comparator is on? The mismatch data can be inserted in a simulation as an ideal element.

If the comparator is a chip you are buying, then the spec sheet will have that information.

Rule of thumb - bipolar comparators will generally have input referred mismatch of 1-3 mV (some even less) A CMOS comparator will be worse, and is heavily dependent on the size of the transistors used. View attachment 312870

How to find it in a circuit like this?

 

I can't read your schematic because the resolution is too low, but if it is a nominal schematic that is symmetric, there won't be any offset voltage. Offset voltages are due to mismatches in the circuit, so a simulation won't show them unless your schematic models the mismatches. This is usually done via a Monte Carlo simulation.

 

View attachment 312883
How to find it in a circuit like this?

you have a differential pair of input transistors there. Get the size of those transistors, and then go look at the characterization and matching data for the semiconductor process, and that particular size of transistors.

You need foundry data to determine this.

 

Hi hsnake'
Please post your LTSpice asc file.

E

 

Hi hsnake'
Please post your LTSpice asc file.

E

 

I can't read your schematic because the resolution is too low, but if it is a nominal schematic that is symmetric, there won't be any offset voltage. Offset voltages are due to mismatches in the circuit, so a simulation won't show them unless your schematic models the mismatches. This is usually done via a Monte Carlo simulation.

Yes, that I know but what should I plot monte carlo of? What variable to use for it? I changed the threshold voltage of pmos and nmos and applied mc function with tolerance. What will be the next step?

 

Were you able to find the offset voltage in this?

 

Hi hsnake'
Please post your LTSpice asc file.

E

were you able to find the offset voltage??

 

Hi,
I am unable to clearly read your asc file, the lettering is too small.
E

 

Hi,
I am unable to clearly read your asc file, the lettering is too small.
E
View attachment 313320

The one on the left is the model file for 45nm. Are you not able to zoom in on the circuit, or see the model file by double clicking on it?

 

Hi,
I am unable to clearly read your asc file, the lettering is too small.
E
View attachment 313320

I have attached the schematic again by removing the model files and have separately attached it. Please look into it now.

 

When you get done with trying to simulate all this it's going to come down to the mismatch of the differential pair at the input.

The answer to the question here is going to come from matching data associated with the process data for those two transistors.

You can plug variance of those devices into the simulator all you want. But it won't be meaningful unless it's based upon empirical data from the foundry.