# Offset voltage comes to saturation in coupling amplifier circuit using OpAmp with Gain=100

#### MrAl

Joined Jun 17, 2014
8,553
V1 is top input and V2 for bottom input..As you see..If i vary R4 and stablize others,the difference between V02 and V01 will change to obtain desired gain....But problem here is to eliminate offset voltage..you know..when i ground V1 and V2 and U1 , U2 comes to saturation..It's weird.That's why I create this post
Hi,

Try a different simulator.

#### Nhơn Nguyễn

Joined May 21, 2019
15
Hi,

Try a different simulator.
Hi,

Try a different simulator.
Vo1-Vo2 is right when I apply my equation and compare with simulation result..But in fact,Vo1 and Vo2 is saturated

#### MrAl

Joined Jun 17, 2014
8,553
Vo1-Vo2 is right when I apply my equation and compare with simulation result..But in fact,Vo1 and Vo2 is saturated
Hi,

Well what i get is when i apply 2v and 1v i get 2v differential before the gain of 50 amp which is right.

Now if you say Vo1-Vo2 is right then how can Vo1 and Vo2 be saturated?
If Vo1 and Vo2 were both saturated you'd see 0v differential so Vo1-Vo2 can not be right.

Yes i proved your result equation was correct too. But what you say now about Vo1 and Vo2 does not make sense.
Maybe you can explain a bit more.

#### Nhơn Nguyễn

Joined May 21, 2019
15
Hi,

Well what i get is when i apply 2v and 1v i get 2v differential before the gain of 50 amp which is right.

Now if you say Vo1-Vo2 is right then how can Vo1 and Vo2 be saturated?
If Vo1 and Vo2 were both saturated you'd see 0v differential so Vo1-Vo2 can not be right.

Yes i proved your result equation was correct too. But what you say now about Vo1 and Vo2 does not make sense.
Maybe you can explain a bit more.
i also don't know the reason why ...so I had you help..And the actual result of difference between Vo1 and Vo2 is approximately 7mV..It maybe alright but when it gets through OA3 then the error will become 7x50=0.35V

#### MrAl

Joined Jun 17, 2014
8,553
i also don't know the reason why ...so I had you help..And the actual result of difference between Vo1 and Vo2 is approximately 7mV..It maybe alright but when it gets through OA3 then the error will become 7x50=0.35V
Hello again,

Ok then what you will have to do is post the circuit with the DC voltages at each node. That is the only way we can tell what is wrong.

If it is the offset voltage adjustment then it may be the wrong values for the pot and associated resistors. We can take a look at that, but first post your circuit again with all the DC voltages at each node and we can go from there.

#### LvW

Joined Jun 13, 2013
1,337
Hi,

Well what i get is when i apply 2v and 1v i get 2v differential before the gain of 50 amp which is right.

.
MrAl - may I ask you HOW did you get these results?
I have simulated the given circuit - and the result was : Saturation, as reported by the questioner.
Note: We must use TRAN simulation (time doman) to reveal instability.....DC simulation gives wrong results (simple example: Opamp with positiive feedback shows a stable bias point in DC simulation)

#### Nhơn Nguyễn

Joined May 21, 2019
15
MrAl - may I ask you HOW did you get these results?
I have simulated the given circuit - and the result was : Saturation, as reported by the questioner.
Note: We must use TRAN simulation (time doman) to reveal instability.....DC simulation gives wrong results (simple example: Opamp with positiive feedback shows a stable bias point in DC simulation)
Hi LvW..TRAN simulation?What does it means?A simulaton tool or something else?

#### MrAl

Joined Jun 17, 2014
8,553
MrAl - may I ask you HOW did you get these results?
I have simulated the given circuit - and the result was : Saturation, as reported by the questioner.
Note: We must use TRAN simulation (time doman) to reveal instability.....DC simulation gives wrong results (simple example: Opamp with positiive feedback shows a stable bias point in DC simulation)
Hi,

Yes thanks, i was thinking that too, but never got back to it. As i stated in my other post i used pure linear analysis and did not check for latch up. But then i was hearing some contradictory results from the OP so i thought i would ask a few questions first.
If i knew all of his findings, each node voltage, i could tell for sure if it was a latch up or not.
I also dont know if the teacher wants him to assume pure linear or not either. And in a time domain analysis, there are usually conditions that can be set to get rid of the latchup. But i'll look more at this too, and especially after he reports back the node voltages.

OK just tried it with MicroCap. I used nearly ideal op amps and put 100pf caps across output to inverting input for both op amps. The result was 2.5v on the top output and 0.5v output on the bottom, same as i got with the linear analysis. So the difference is again 2.000v and of course that would get amplified by 50 which would normally pin the output of the last op amp, but i use nearly ideal power supplyless op amps so the output just goes to nearly -100v.

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#### LvW

Joined Jun 13, 2013
1,337
Hi LvW..TRAN simulation?What does it means?A simulaton tool or something else?
TRAN is an abbreviation for "Transient Analysis", which means an analysis inthe time domain (rather than frequency domain)

#### Nhơn Nguyễn

Joined May 21, 2019
15
TRAN is an abbreviation for "Transient Analysis", which means an analysis inthe time domain (rather than frequency domain)
/
OK..So how can you analyze with it?Can you show me specific process?

#### LvW

Joined Jun 13, 2013
1,337
A kind of summary:
The opamp U1 has a pure resistive negative feedback loop and another positive feedback loop involving the amplifier U2.
However, this second feedback loop is internally unstable (because it has a local dominating positve feedback).
Hence, the whole system cannot be used as an amplifier because it has no stable operating point..

Comment: Due to symmetric properties of the circuit, the above explanation is true also if we replace U1 by U2 and vice versa.

#### MrAl

Joined Jun 17, 2014
8,553
Hi LvW,

Perhaps you can show some analysis as to how you did this circuit in order to determine what you did.

Op amps can have positive feedback though without latching up.
An example for one circuit in the time domain shows this exponential factor in the response function:
e^(-(t*(R1*R4-R2*R3))/(C1*R1*R2*R4))

and here we can see that when R1*R4>R2*R3 we get a stable response, but when R2*R3>R1*R4 we get a saturated output condition.

Positive feedback is often used to raise the input impedance of an op amp circuit or to increase the gain of a stage.

The circuit in hand here has positive feedback that's true, but there may be certain conditions that allow it to work normally. This could be based either on the choice of values or the choice of initial conditions.

#### LvW

Joined Jun 13, 2013
1,337
Hi LvW,

Perhaps you can show some analysis as to how you did this circuit in order to determine what you did.
....................
Op amps can have positive feedback though without latching up.
.....................
The circuit in hand here has positive feedback that's true, but there may be certain conditions that allow it to work normally. This could be based either on the choice of values or the choice of initial conditions.
Yes - its true that the appearance of a positive feedback loop does not necessarily mean that the whole circuit must be unstable - BUT:
In such a case, there must be in addition a dominating negative feedback (so that the net feedback is still negative).
More than that, a net positive feedback could be allowed if the pos. loop gain is below unity.

However, this does not apply to the shown circuit.
For the amplifier U2 the negative feedback factor is kn=15/(15+120)=0.111 ; the positive feedback factor is kp=15/(15+15)=0.5.
That means: The pos. loop gain is LG=0.5*(1+120/15)=4.5.
Hence, pos. feedback is dominating (with a loop gain >1) and the whole feedback network for U1 (involving U2) is unstable.

#### Nhơn Nguyễn

Joined May 21, 2019
15
Yes - its true that the appearance of a positive feedback loop does not necessarily mean that the whole circuit must be unstable - BUT:
In such a case, there must be in addition a dominating negative feedback (so that the net feedback is still negative).
More than that, a net positive feedback could be allowed if the pos. loop gain is below unity.

However, this does not apply to the shown circuit.
For the amplifier U2 the negative feedback factor is kn=15/(15+120)=0.111 ; the positive feedback factor is kp=15/(15+15)=0.5.
That means: The pos. loop gain is LG=0.5*(1+120/15)=4.5.
Hence, pos. feedback is dominating (with a loop gain >1) and the whole feedback network for U1 (involving U2) is unstable.
So do you have any suggestion for me ?Personally..I think it is impossible to make it work since apart from what you mention above,non inverting input is also connected to unstable source and it maybe a additional reason for its unstability

#### MrAl

Joined Jun 17, 2014
8,553
Yes - its true that the appearance of a positive feedback loop does not necessarily mean that the whole circuit must be unstable - BUT:
In such a case, there must be in addition a dominating negative feedback (so that the net feedback is still negative).
More than that, a net positive feedback could be allowed if the pos. loop gain is below unity.

However, this does not apply to the shown circuit.
For the amplifier U2 the negative feedback factor is kn=15/(15+120)=0.111 ; the positive feedback factor is kp=15/(15+15)=0.5.
That means: The pos. loop gain is LG=0.5*(1+120/15)=4.5.
Hence, pos. feedback is dominating (with a loop gain >1) and the whole feedback network for U1 (involving U2) is unstable.
Hi,

That makes sense, a lot of sense, but then i guess we have to look at why placing two 100pf caps across each feedback resistor allow the transient response to show the same as the regular DC analysis.
I dont know if i will get time to do this for now i have some very important things going on.

#### LvW

Joined Jun 13, 2013
1,337
.......... i guess we have to look at why placing two 100pf caps across each feedback resistor allow the transient response to show the same as the regular DC analysis.
...................
.
Hi again,
I think the most secure method for revealing possible saturation effects is to use (at least) one ramping power supply, which reaches the final value Vcc after some milli-seconds. Thats what I did to prove saturation - and there was no diffreence between with/without capacitors across the feedback resistors.