Hi, I am having a hard time trying to analyze the circuit below:
It is said that the output (9V_currentLImited) is well 9V with a 30mA current limitation. capacitors C2, C3 and C4 are electrolytic capacitors while C1 is the non-electrolytic type. V1 is a 9V voltage source.
What I have tried to understand so far is that the NMOS (M1) source is supplying a slightly less than 9V due to the property of NMOS which then powers the Base of Q2. But, I have a hard time trying to calculate where does the 30 mA current limitation comes from?
Next question, what does the capacitors take part in this circuit?
Thanks!
It is said that the output (9V_currentLImited) is well 9V with a 30mA current limitation. capacitors C2, C3 and C4 are electrolytic capacitors while C1 is the non-electrolytic type. V1 is a 9V voltage source.
What I have tried to understand so far is that the NMOS (M1) source is supplying a slightly less than 9V due to the property of NMOS which then powers the Base of Q2. But, I have a hard time trying to calculate where does the 30 mA current limitation comes from?
Next question, what does the capacitors take part in this circuit?
Thanks!