I'm looking for a circuit whose output stays on for a while after the input has gone, but in negative logic.

I know a 555 timer or an RC + transistor circuit works with positive logic, but I don't know what works with negative logic.

In other words, a circuit whose output goes LOW as soon as the input goes LOW, but stays LOW for a bit after the input goes HIGH (or Hi-Z).
Preferably, I'd want it to work with Hi-Z (without pullup resistors).
It should stay for 2-3 seconds.

It will connect to a button, which connects to ground when closed. I can't really make the button connect to power when closed.

This is how the timing would work:

 

1. What is the power supply voltage for the circuit?

2. What is the input signal voltage range?

3. What is the output signal voltage range?

4. What will the output of the delay circuit drive - a downstream circuit, or device, or what?

5. How fast does the output rising edge have to be? IOW is there a maximum risetime spec?

6. What is your skill set for assembling a circuit. Through-hole components? Surface mount?

7. What is the minimum time between when the input signal goes low and when it goes high?

ak

 

I know a 555 timer or an RC + transistor circuit works with positive logic, but I don't know what works with negative logic.

Version using a cmos 555.
When power is first applied the output remains Low for the delay time required determined by C1, R1 and R2.
Now anytime Sw1 is closed the output goes Low and remains Low for the delay required after Sw1 is released.

 

Any monostable multivibrator circuit in 7400 family or 4000 family.

 

Version using a cmos 555.

For the TS - Pin 6?

ak

 

For the TS - Pin 6?
ak

What about pin 6?

 

It's not shown in #3, so the Threshold input is - floating - ?

ak

 

It's not shown in #3, so the Threshold input is - floating - ?
ak

Correct, left floating.
I suppose it should be connected to ground as well.

 

1. What is the power supply voltage for the circuit?

2. What is the input signal voltage range?

3. What is the output signal voltage range?

4. What will the output of the delay circuit drive - a downstream circuit, or device, or what?

5. How fast does the output rising edge have to be? IOW is there a maximum risetime spec?

6. What is your skill set for assembling a circuit. Through-hole components? Surface mount?

7. What is the minimum time between when the input signal goes low and when it goes high?

ak

1. 5V
2. 5V/Hi-Z - 0V
3. The output should be grounded
4. It would drive a digital input pin, no big load
5. It doesn't really matter, but it should rise instantly. Same with the falling edge.
6. I'd prefer THT, but I really only care about the component count.
7. The input signal would be high (so 0V) for at least 10 ms (but usually 100 ms)

This is how I'd want it to behave (if I wasn't clear):

 

Version using a cmos 555.
When power is first applied the output remains Low for the delay time required determined by C1, R1 and R2.
Now anytime Sw1 is closed the output goes Low and remains Low for the delay required after Sw1 is released.
View attachment 343045

Yeah, the 74LS121 seems appropriate for me.

 

Yeah, the 74LS121 seems appropriate for me.

Actually, it doesn't.

 

I think a Schmitt trigger that sinks the output + an RC circuit would be just fine for this project.

 

6. I'd prefer THT, but I really only care about the component count.

Post #3 only uses 5 components.

 

1. 5V
2. 5V/Hi-Z - 0V
3. The output should be grounded
4. It would drive a digital input pin, no big load
5. It doesn't really matter, but it should rise instantly. Same with the falling edge.
6. I'd prefer THT, but I really only care about the component count.
7. The input signal would be high (so 0V) for at least 10 ms (but usually 100 ms)

This is how I'd want it to behave (if I wasn't clear):

View attachment 343052

Several of your responses need more discussion and clarification. For example, in #3 you say the output should be grounded. I know you don't mean that the output should be shorted to grounded, so what do you mean? Do you mean that the output low state voltage should be near 0 V? If so, that what is the desired output high state voltage?

But the biggie is your new timing diagram. It changes *everything*.

The two short-time inputs imply that there is a minimum time the input must return high for, before the output begins its time delay. If so, what are the minimum and maximum pulse widths that the circuit should ignore?

ak

 

I think a Schmitt trigger that sinks the output + an RC circuit would be just fine for this project.

A Schmitt trigger circuit will be a part of the solution, but it will take a lot more to meed the timing requirements in post #9. What are the two short input pulses?

ak

 

A Schmitt trigger circuit will be a part of the solution, but it will take a lot more to meed the timing requirements in post #9. What are the two short input pulses?

ak

I think the TS means after the first press of the switch and then if it goes high again for a time less then the delay period then the output remains low.

 

Use 74LS123.

 

A Schmitt trigger circuit will be a part of the solution, but it will take a lot more to meed the timing requirements in post #9. What are the two short input pulses?

ak

The two short pulses are to demonstrate that the input stays HIGH (0V) if the input is released for little while.
I don't have precise timing requirements, 1.5-5 seconds is fine by me, cause it's just a small project.

If there is another problem with the idea of a Schmitt trigger with an RC circuit, please let me know.

 

Several of your responses need more discussion and clarification. For example, in #3 you say the output should be grounded. I know you don't mean that the output should be shorted to grounded, so what do you mean? Do you mean that the output low state voltage should be near 0 V? If so, that what is the desired output high state voltage?

But the biggie is your new timing diagram. It changes *everything*.

The two short-time inputs imply that there is a minimum time the input must return high for, before the output begins its time delay. If so, what are the minimum and maximum pulse widths that the circuit should ignore?

ak

The minimum pulse width is 0 seconds, and the maximum pulse width is the 2-3 seconds.

The desired HIGH state is sinking (it drives an active low input), and the desired LOW state is Hi-Z or 5V (doesn't matter as long as it isn't sinking).

Correct me if I'm wrong please, but I think this is achievable with an RC + comparator or inverted Schmitt trigger + transistor trigger circuit.
A HIGH (0V) state on the input would charge the capacitor instantly, making the output HIGH, and a LOW (Hi-Z or 5V) state would slowly discharge it, eventually discharging it enough to make the output LOW again.

 

On a component count basis why isn't my circuit in post #3 sufficient?