# Need help in designing bistable circuit

#### sanmeet hundal

Joined Mar 25, 2015
2
Dears, I have been racking my brains to design a small analog circuit but with no success. I hope some genius will point me in the right direction.
The problem: I have (say) 12V DC power supply. I need a circuit sensing the output DC of the power supply and which will give a high output when Power supply is switched OFF and then ON within (say) 3 seconds. If the power supply is switched ON after more than 3 seconds of last OFF than I need a low output. Anyone can help?

#### sanmeet hundal

Joined Mar 25, 2015
2
More details on the above question:
Broader problem: I am trying to design a bulb with two strings of LED of different colours. The bulb should run colour-A/LED String 1 when it is switched ON after a long time (say after 3 seconds of last turn OFF). When the bulb is turned ON within 3 seconds of turning OFF then the colour B LED/LED String 2 should glow. So I will have a bulb with two possible colours that can be chosen with a single power switch.
I have tried to design with a RC and opamp. RC takes 3-5 seconds to charge/discharge, so when power is switched ON within 3 seconds of last OFF, I will have a voltage on the capacitor indicating the switch is turned ON within 3 seconds of last turn OFF. But Im not able to get a stable output to run the two FETs in the two colour LED strings. Any help would be highly appreciated.

#### AnalogKid

Joined Aug 1, 2013
8,138
What powers you monitor circuit while the power supply is off?

ak

#### Alec_t

Joined Sep 17, 2013
10,438
Something based on this perhaps?

When the switch closes, C1/2/3 all charge up. C3 holds up the supply voltage Vdd for U1 (a CD4013 dual flip-flop) if the switch then opens again briefly. After ~3 secs the C2 voltage is enough to set flip-flop U1a, thus clocking U1b. The U1b outputs thus depend on whether the C1 voltage at that time is high or low, which in turn depends on whether the switch has been opened or not. Q1 discharges C1 each time the switch opens. D2 prevents the U1b data input being significantly above Vdd at power-down.

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