http://i.imgur.com/NPPnaD0.jpg (Fig. for the Counters)

I need some help on figuring out how to find the output frequencies (Q0-Q3) for these two counters, which are made up of 2, 4-Bit Binary IC 74LS293 chips. Which formulas can I use in this situation? Any assistance is most definitely appreciated!

 

The best you can do is make a table of states to see what the behavior is.

 

those chips are binary counters so each stage divides by two (unless MR inputs are causing reset...). also chip has two separate counters, one has only single stage (input CP0' and output Q0), second counter has three stages (input is CP1' and outputs are Q1, Q2, Q3). counters can be cascaded of course.

input signal is first going through 3-stage counter (input is Z1.CP1' and output is Z1.Q2), since output is taken from Q2 (second stage) ...

 

Please post your circuit diagram in your post (or attached to your post) instead of a link to a 3rd part site that may or may not be available right now or a year from now. Please keep the file size to a few hundred kilobytes if at all possible (and it is almost always possible to make them MUCH smaller than that).