I am working on a lab where we created a basic ALU that adds/subtracts or does an AND operation. It does this using a standard 4-bit ripple carry adder that can decide when to subtract using 2's complement based on the initial cin. Now I have a problem that says:
If we wanted to extend our ALU design with a signal that is HIGH when A ≥ B, what
changes could we make to the design to do so? Include a gate-level schematic with your suggested
modifications. Hint: Think about the sign bit of the result when performing a subtraction.
I realize I could just do the truth table/k-map thing, but with this having 8 inputs that would be huge and overly complex. I currently know how to output how when A=B by just doing A1 (XOR) B1 with each of the bits and ANDing them together. I'm not sure how to incorporate the > part though.
Also I realize you could just invert the most significant bit, and this would work when you are subtracting, but when you add a number where A<B then it wouldn't work properly. Any kind of help would be appreciated.
(I would upload pictures of my circuits but don't know how to attach a photo from my computer onto this post.)
If we wanted to extend our ALU design with a signal that is HIGH when A ≥ B, what
changes could we make to the design to do so? Include a gate-level schematic with your suggested
modifications. Hint: Think about the sign bit of the result when performing a subtraction.
I realize I could just do the truth table/k-map thing, but with this having 8 inputs that would be huge and overly complex. I currently know how to output how when A=B by just doing A1 (XOR) B1 with each of the bits and ANDing them together. I'm not sure how to incorporate the > part though.
Also I realize you could just invert the most significant bit, and this would work when you are subtracting, but when you add a number where A<B then it wouldn't work properly. Any kind of help would be appreciated.
(I would upload pictures of my circuits but don't know how to attach a photo from my computer onto this post.)