I’m currently working on a ceramic substrate trace design calculator (focused on trace width and spacing for power applications), and I’d really appreciate some feedback from people with experience in PCB / DBC / AMB / power module design.

The calculator considers factors like:

• Current carrying capacity
• Thermal constraints
• Substrate material (e.g., Al₂O₃ / AlN)
• Trace spacing rules for high voltage

I’ve shared the calculator link in the comments below—would really appreciate any feedback!

Before refining it further, I’d love to sanity-check the methodology and results:

• Do the calculated trace widths look reasonable for given currents?
• Are the spacing assumptions aligned with what you typically use in high-voltage designs?
• Any obvious mistakes or missing parameters?
  

Any feedback—whether detailed or just a quick impression—would be hugely appreciated. Thanks in advance!

 

I’m currently working on a ceramic substrate trace design calculator (focused on trace width and spacing for power applications), and I’d really appreciate some feedback from people with experience in PCB / DBC / AMB / power module design.

The calculator considers factors like:

• Current carrying capacity
• Thermal constraints
• Substrate material (e.g., Al₂O₃ / AlN)
• Trace spacing rules for high voltage

I’ve shared the calculator link in the comments below—would really appreciate any feedback!

Before refining it further, I’d love to sanity-check the methodology and results:

• Do the calculated trace widths look reasonable for given currents?
• Are the spacing assumptions aligned with what you typically use in high-voltage designs?
• Any obvious mistakes or missing parameters?

Any feedback—whether detailed or just a quick impression—would be hugely appreciated. Thanks in advance!

I’m currently working on a ceramic substrate trace design calculator (focused on trace width and spacing for power applications), and I’d really appreciate some feedback from people with experience in PCB / DBC / AMB / power module design.

The calculator considers factors like:

• Current carrying capacity
• Thermal constraints
• Substrate material (e.g., Al₂O₃ / AlN)
• Trace spacing rules for high voltage

I’ve shared the calculator link in the comments below—would really appreciate any feedback!

Before refining it further, I’d love to sanity-check the methodology and results:

• Do the calculated trace widths look reasonable for given currents?
• Are the spacing assumptions aligned with what you typically use in high-voltage designs?
• Any obvious mistakes or missing parameters?

Any feedback—whether detailed or just a quick impression—would be hugely appreciated. Thanks in advance!

I’m currently working on a ceramic substrate trace design calculator (focused on trace width and spacing for power applications), and I’d really appreciate some feedback from people with experience in PCB / DBC / AMB / power module design.

The calculator considers factors like:

• Current carrying capacity
• Thermal constraints
• Substrate material (e.g., Al₂O₃ / AlN)
• Trace spacing rules for high voltage

I’ve shared the calculator link in the comments below—would really appreciate any feedback!

Before refining it further, I’d love to sanity-check the methodology and results:

• Do the calculated trace widths look reasonable for given currents?
• Are the spacing assumptions aligned with what you typically use in high-voltage designs?
• Any obvious mistakes or missing parameters?

Any feedback—whether detailed or just a quick impression—would be hugely appreciated. Thanks in advance!

https://creamicpcbmanufacture.com/contact-us-trace-spacing-and-width-calculator/