hey guys listen i got a project that requires me to build a 2stage amp(Voltage devider, pnp)1 that amplifies the input as voltage by 1000.....1st stage is a common base and 2nd stage is common emitter....... well i tried numerous designs but not one work ...... maybe i am using the wrong formulus.. plz can someone help .............

 

post your circuits and working out.

 

how do i upload the document and my cct diagram?

 

how do i upload the document and my cct diagram?

On the Reply to Thread page, scroll down to the Additional Options section and select Manage Attachments. The pop-up window will allow you to select files from your computer. When you select Upload, it uploads the file(s) to the end of the post.

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Dave

 

ok heres the correct files i just print screened the things and pasted it into a jpeg file

 

right can no1 help?

 

you must increase the frequency of ur signal generator.
Those coupling caps are going to have a VERY high reactance at 1hz

 

Freq response is part of the issue. Looking at the schematic...

Voltage gain is Rc/Re , not taking loading into account.

There is also another problem, you said you want a gain of 1K? Most transistors have a beta (β) of between 10 to 100. This is the gain you will get, it is the max the transistor is capable of. You can gang them together as in a Darlington configuration, which will multiply the gains of the transistors together. Two betas of 50 will create a beta of 2500, but this is DC gain, and will roll off quite fast.

A third issue is your DC emitter resistance to base resistors is too extreme. You have 500Ω emitter resistance. If the transistor β is 50 then you have a base-emitter load resistance of 2500Ω (2.5KΩ), this will swamp the 15KΩ you have in parallel.

 

no big deal there. It seems his design constraint is to use 2 cascaded stages, one common base the other common emitter. A gain of ~32 for both stages will produce a total gain of ~1000.

 

I don't remember the formula's off hand, but common base gains are quite low, and common collector is unity. Common emitter is the voltage gain configuration, and the way he has it set up transistor beta is the limiting factor. Reread his post, common base for the first amp.

I have my weaknesses, but common emitter designs I have down.

 

the transistor im using is BC107B it has a beta average of 300......AC and DC.. how do i determine the capacitors i a need to use?

And can u guys check if formula's correct for the 2nd stage(Common Emitter)
Rc = (RL*RC)/(RL+RC)
A'v = Rc/(RE1
R2 <= ((Beta+1)*RE)*0.1
R1:
VB = (R2/(R1+R2))*Vcc

 

This is pretty straight forward, the impedance of the cap should be around 1/10 the input resistance. Assuming a beta of 300 (and this sounds a bit high) you're input impedance is around 15KΩ along with the other base resistors your input is around 7KΩ. If you want to handle 1Hz then figure the capacitance needed for 700Ω at 1Hz.

The same rules apply for your emitter swamping capacitor and your output capacitor.

AC beta IS NOT a constant. It rolls off until it's unity gain frequency, so don't make the mistake of thinking AC beta is either flat or 300. The gain of your amp will be flat until the beta drops below the gain the circuit sets it for, then it (AC gain) will start rolling off according to the transistor.

You're gain is going to be (3.2KΩ//10KΩ)/250Ω, or somewhere around 2.5KΩ/250, or around 10. Is this what you're asking? I use the // to show resistors in parallel.

I've got to step out for the day, I'll be glad to go through the math later.

 

The hertz was just to let the graph be displayer correctly, i will probaly use 100Hz as my input freq. Well acording to the data sheet for BC107B Beta min = 250 and beta max = 450 so my beta avg is 300. so if i assume that my CE amp will have a gain of 10 my resistors are as follows for my 2nd Stage CE AMP: Rc = 2.5k,RC = 3.3K,RE = 500 (RE1 = 250,RE2 = 25),R1 = 82K,R2 = 15K. does it look correct?

 

With Ic @2mA, Vce=5, Vf=1kHz, hFE (typical) = 300; min = 200, max = 450.
http://www.datasheetcatalog.org/datasheet/stmicroelectronics/9293.pdf

Try using 1kHz for your input signal frequency.

 

The mathematical side seem alright.
Without any specific information on the source and load impedance it's a little difficult to steer you through the design.

How have you gone with the common base (1st stage)?

If i were you i would design this first. I had a quick go at common base bjt circuits and i built a circuit with a voltage gain of 200.

If you're unfamiliar the e-book on this site has a good write up on common base circuits.

 

Here is a link to the common-base amp stage to which s_lannan referred.

hgmjr

 

S_lannan could u show me the disgn of that common base amp of urs that had a voltage gain of 200. i just want to check how u built it using voltage divider cicuits and im really struggling to get this circuit to work.........

 

I have my weaknesses, but common emitter designs I have down.

I don't think so.

Most transistors have a beta (β) of between 10 to 100. This is the gain you will get, it is the max the transistor is capable of. You can gang them together as in a Darlington configuration, which will multiply the gains of the transistors together. Two betas of 50 will create a beta of 2500, but this is DC gain, and will roll off quite fast.

A darlington has a high current gain, but the same voltage gain as an ordinary single transistor. Voltage gain has nothing to do with beta.
Beta affects the input impedance.

 

Sorry for the double-post but I didn't see the 2nd page until now.

A BC107 transistor has a gain-bandwidth product of typically 300MHz. It will still have plenty of current gain at 30MHz. It will have plenty of voltage gain at 10MHz.

Gusmas doesn't want a cascaded common-base driving a common emitter because it has an extremely low input impedance.
Instead he wants a cascode pair:

 

looks like im screwed......