Here is something I did last year for another thread. You can adjust the times to fit your application. You might not need the output transistor. And one of the unused gates can be used to invert the output signal if you need the other logic polarity.

U1B acts as an inverting-input OR gate - if either input is low, the output goes high.

R1-C1 sets the time for the first pulse.

R2-C2 sets the time for the gap between pulses. It is running during the first pulse, holding off the second pulse, so its time is the first pulse time plus the desired inter-pulse gap.

R3-C3 sets the time for the second pulse.

Each pulse time is approx. 0.9 x R x C.

For your application, leave all caps at 2.2 uF (ceramic or metal film preferred).
R1 = 470 K >> 0.9 sec. first pulse
R2 = 1.0 M >> 1.3 sec. gap
R3 = 1.0 M >> 2.2 sec. second pulse

If you don't have a 4093, a variation of this circuit uses a hex inverter, but it adds two small signal diodes to perform the OR function.

UPDATE: I sounds like when power goes off, the power input is open circuit. This means there is no discharge path to reset the capacitors. Place a 10K resistor across Vcc and GND. C2 should discharge through the unused gates input protection circuits. If it doesn't, add a 470K resistor from U1A pin 3 to Vcc.

Here is an updated schematic.

ak

 

I think I'm done now. Here is a re-work that makes all three periods independent.

R1-C1 sets the time for the first pulse.

R2-C2 sets the time for the gap between pulses.

R3-C3 sets the time for the second pulse.

ak

 

OOOhhh I just saw something. I can get rid of the OR gate function. Working through the pulse polarities, R3-C3 are active and making an output pulse at power-on, at the same time as R1-C1. This is not a problem, because when the 2nd timer starts it truncates the third timer's output pulse. So disconnecting pin 9 from pin 2, and connecting it to pin 8, should have no effect on the output pulse sequence. Hmmm ...

ak

 

OK, now I'm done.

When power first is applied, there is zero volts across all three timing capacitors. U1A's input is low, so its output is high. R2 holds the right side of C2 high, so there is zero volts across it. U1B's output is low, so C3 starts charging through R3. This causes U1C to produce the first output pulse.

R3-C3 makes the first output pulse, but it is truncated by the R1-C1 timer - U1A input goes high, output goes low, pulling U1B inputs low, forcing its output high, ending the R3-C3 timing cycle - so R1-C1 is actually setting the first pulse width. When C1 is charged up above the positive-going transition level, U1A's output goes low, initiating the gap timer. At the end of the gap, U1B's output goes low, initiating the output timer again. This time it runs its full time.

BTW, RCA designers used to call this kind of pulse former a "boxcar" circuit.

ak

 

Thanks Eric. I'll alter the circuit and get back to you. Tony

Works just fine Eric. Very many thanks. Tony

 

Thanks AnalogKid. I'll have a look at building this if I can't solve it with the 555 circuit.

 

74 soldered pins vs. 32. Just sayin ...