NAND flash interface - how does it work?

Thread Starter

turboscrew

Joined Dec 7, 2018
16
It looks like I have to use STM32F4xx FMC NAND interface to handle an LCD display, because the NOR interface has too short data hold time. The problem is, that I don't know how the NAND interface works. I need to know to misuse it properly.
(I got it to work, but had to slow down the processor from 180 MHz to 90 MHz.)

Google hasn't been my friend on this. What I've found are about "how wonderful they are" and what kind of semiconducting layers they are made of.

The little understanding I have got is that it usually works "below" RAM: you can write in the RAM (covering a page) and then write the page into the NAND, and read a page from NAND to RAM and pick bytes from the RAM. I wonder if this is anywhere near correct idea?

I'd also like to get pointers to somewhere that I could learn more about how the interface works.
 

dl324

Joined Mar 30, 2015
14,302
Welcome to AAC!

NAND FLASH are more difficult to use than NOR. You always need to add error correction because NAND are typically shipped with bad bits that need to be marked and bits go bad during normal operation; so not only do you need to detect and correct errors, you also need to mark new bad blocks.

EDIT: correction - bad bits found during electrical test in the factory are already marked bad.

Read/write information should be available in the datasheet.

Attached is an article contrasting NOR vs NAND, and a Micron datasheet.
 

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Thread Starter

turboscrew

Joined Dec 7, 2018
16
Thanks. The datasheet may contain a lot of what I'm after. I only browsed the links, but I'll dig deeper into them.
I don't have to worry about error correction, because I won't be using any NANDs, just the interface to control an LCD.
 

mckenney

Joined Nov 10, 2018
124
It looks like I have to use STM32F4xx FMC NAND interface to handle an LCD display, because the NOR interface has too short data hold time. The problem is, that I don't know how the NAND interface works. I need to know to misuse it properly.
The NAND model includes a backing storage array and a one-page cache register. What you do with it is some subset of (a) read a page into the cache (b) manipulate the data in the cache (c) write the cache out to the array. The cache isn't directly visible to the host, you fetch/store data through the bus. There are (presumed) bad blocks, and someone has to compute an ECC (I'll pay extra for the chip to do it).

But that's not what you need the FMC for. You want it for the low-level bus twiddling. The bus recognizes Commands (CLE) Addresses (ALE) and Data (neither). The Write Enable (WE) allows you to present data to the bus, and OE accepts data from the device.There's a byte-ordering convention (big-endian, as I recall). The bus protocol is a small (but somewhat scattered) part of a Micron data sheet; I'm hoping some keywords will help you find them. There was enough information in a Micron data sheet for me to implement an 8-bit bus-banging host.

[I'm working from memory here. Listen to what the data sheet says, not what I say.]
 

Thread Starter

turboscrew

Joined Dec 7, 2018
16
Yes. What I've learned from the datasheet helped me to understand the FMC documentation and vice versa.
There's still things to learn, but I think I've grasped the very basics of the bus, but also of the NANDs.
It looks doable, but the FMC only supports caches upto 64kB, so with 16-bit pixel QVGA (320x240 pix) the data needs to be written in 4 pieces. In a sense, LCD controller works the same way as the NAND: you set the write address and start writing the data. The address autoincrements in the LCD controller.
 
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