Hi there.

Im developing a PMOS ring oscillator. On the end of this oscillator i've set up an amplifier to convert the oscillating signal to a square wave. This circuit has been simulated in LTspice, as follows:



Now in Spice, the square wave switches between 0 and 0.6 volts. Although as you can see below, when i mimic this circuit on a breadboard, i get a square wave which switches between 0 and 4.1 Volts (which is better for my application ofcourse).

Can anyone explain why the difference between the voltages in simulation and in practice is so big?

Thanks in advance!

 

See
Error 15%.
If we make a more accurate model of the transistor (parameters for nonlinear capacitances), using the capabilities of the built-in model of VDMOS, we can get more impulses that are more similar to reality.

 

Thanks a lot again.

Well i just noticed my problem about the 'small' square wave... My second transistor was just rotated wrong.

Now i got it working like yours, as you can see:


But still i got the problem that the oscillating frequency is around 6061 Hz, while in my simulation the frequency of the square wave is around 3891 HZ.



Do you have any idea how to improve the accuracy of my simulation?

By the way, the VDMOS function or capacitor(s) wont influence my frequency.

Thanks!

 

Hi

The pmos transistors are connected backwards.
Source should connect to positive and drain to ground.

eT

 

See

 

yeah so i wanted to show you, (just realized that i haven't been really clear about that) that the VDMOS function (cshunt) and capacitor don't influence the frequency. Although when i mimic this circuit on a breadboard, exactly the same way, i end up with a frequency of about 6000 Hz. Which is almost twice as high as the simulated frequency. Now for my schoolreport, i need to verify this frequency of 6000 Hz with a simulation. Is there any way to do an more accurate simulation in LTspice?

Thanks!

 

Since you said that the ring oscillator, but I can't find any where has ring?

 

in the left bottom corner, A6 is connected to A1

 

View attachment 142110

in the left bottom corner, A6 is connected to A1

I saw it, but it's unclear, next time maybe you can separate the circuit and waveform to two pictures, and make sure the circuit is clear.

 

I saw it, but it's unclear, next time maybe you can separate the circuit and waveform to two pictures, and make sure the circuit is clear.

Yeah i can understand, will do next time!

 

My model:
.model irlib9343_AB VDMOS pchan Vto=-2.2 KP=9.51 Lambda=16.6m Cgso=620p Cjo=388p
+ Rb=11m Vj=5 M=0.625 Theta=0.35
+ BV=55 ibv=250u nbv=10 Rds=1Meg RG=5 Rs=73.7m tt=100n CGdmin=38p Cgdmax=1.n
+ a=0.25 ksubthres=100m
See

 

YAASSS, finally the simulations correspond with my circuits! Thanks a lot! I guess my symbol its parameters weren't completely right.

 

My model is more consistent with the datasheet than the factory model.
See

 

So for my next step i'm building an smd ring oscillator, using the BSS84 (http://www.mouser.com/ds/2/196/Infineon-BSS84P-DS-v02_07-en-1226467.pdf)

For now i can find several models for this transistor. How do i know which one in LTspice will be the best at corresponding to a real component?

I've got these models:

.SUBCKT BSS84 1 2 3
* 1=drain 2=gate 3=source
Cgs 2 3 20.6E-12
Cgd1 2 4 56.1E-12
Cgd2 1 4 3.5E-12
M1 1 2 3 3 MOST1
M2 4 2 1 3 MOST2
D1 1 3 Dbody
.MODEL MOST1 PMOS(LEVEL=3 VTO=-1.7 W=12m L=2u KP=10.07u RD=3.952 RS=20m)
.MODEL MOST2 PMOS(VTO=3.25 W=12m L=2u KP=10.07u RS=20m)
.MODEL Dbody D(CJO=45.35p VJ=462.4m M=325.5m IS=442f N=1.051 RS=1.243
+ TT=105n BV=50 IBV=10u)
.ENDS

And

*
.SUBCKT BSS84 3 4 5
* NODES: DRAIN GATE SOURCE
M1 3 2 5 5 MOD1
RG 4 2 167
RL 3 5 50E6
C1 2 5 26P
C2 3 2 4P
D1 3 5 DIODE1
*
.MODEL MOD1 PMOS VTO=-1.709 RS=3.091 RD=0.979 IS=1E-15 KP=0.146
+CBD=12P PB=1
.MODEL DIODE1 D IS=1.072E-13 RS=0.527 N=1.077
.ENDS BSS84
*
*$
*
And
.model BSS84 VDMOS(pchan Rg=3 Vto=-2.1 Rd=2.4 Rs=1.8 Rb=3 Kp=.2 Cgdmax=.04n Cgdmin=.001n Cgs=.02n Cjo=.01n Is=2p mfg=Philips Vds=-50 Ron=6000m Qg=1n)

Besides these models, LTspice also has a bss84 MOSFET built-in at the library.
I hope you could help me develop the same model as for the IRLIB9343. Thanks!

 

.model BSS84 VDMOS(pchan Rg=3 Vto=-2.1 Rd=2.4 Rs=1.8 Rb=3 Kp=.2 Cgdmax=.04n Cgdmin=.001n Cgs=.02n Cjo=.01n Is=2p ksubthres=.1 mfg=NXP Vds=-50 Ron=6000m Qg=1n)
The parameter ksubthres=.1 affected the delay of the gate. This parameter takes into account the subthreshold current of the transistor. For your transistor, 30μA is a low current and the parameter added by me improved the correspondence with reality.
With low-power transistors and 10kΩ load resistor, the speed will be much higher (due to small capacities). For testing models you can use this template: