my answer right or wrong? Q0 &Q1 &Q2 &Q3

 

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Why are you starting yet another thread on this same problem?

Think about what your waveforms are saying. Q0 changes from LO to HI at clock #2 but nothing else changes. Then it changes back to LO at clock #3 placing everything in the exact same state it was in after clock #1. But then, magically, at clock #4 both Q0 and Q2 change. Does that make sense?

Be methodical about your work. Don't scribble notes on the diagram that are impossible to follow. Make a table that shows the D input values and the state changes for each clock.

 

hi full,
Your answer is wrong.
E

 

hi full,
Your answer is wrong.
E

how is right ?!

 

Why are you starting yet another thread on this same problem?

Think about what your waveforms are saying. Q0 changes from LO to HI at clock #2 but nothing else changes. Then it changes back to LO at clock #3 placing everything in the exact same state it was in after clock #1. But then, magically, at clock #4 both Q0 and Q2 change. Does that make sense?

Be methodical about your work. Don't scribble notes on the diagram that are impossible to follow. Make a table that shows the D input values and the state changes for each clock.

the question told you the Q output=1
the intentional Q0 (#clk 0 from 1 in waveform) and (#clk 1 from 0 in waveform) ......
the Q1 J0 - K0 => no change ,all the clks 1.....
my answer Q0 and Q1 it is true
but Q2 and Q3 I don't know true or error!

 

Look at it again ....

Prior to the first clock pulse, all the Q's are 1, all not Q's are 0. So, that portion of your diagram diagram is correct.

At the first positive transition of the clock pulse ... You have only Q0 as changing to 0. Can you explain why Q1, Q2, and Q3 remain as a 1?

 

the question told you the Q output=1
the intentional Q0 (#clk 0 from 1 in waveform) and (#clk 1 from 0 in waveform) ......
the Q1 J0 - K0 => no change ,all the clks 1.....
my answer Q0 and Q1 it is true
but Q2 and Q3 I don't know true or error!

PLEASE! Just use the normal font. We are all capable of reading and don't need the written equivalent of shouting at us.

Shouting or not, I can't really tell what you are trying to say here. Please rephrase it in more detail. I know we are fighting a language issue, but we can get through that eventually.

My recommendation still holds. Make a table that shows the states of the flip flops and the control inputs prior to each rising clock edge. Or, alternatively, show them as additional traces in your timing diagram.

 

I agree with WBahn. Show the state of the control inputs.

 

hi full,

This image should show where you have gone wrong after the 1st Clock pulse.

E

 

I change lines Q2 &Q3

now true?

 

hi,
Sorry, its still not correct.

Consider FF1 input, before the 1st Clock, the JK are both Low. [ because /Q of FF3 is Low]

After the rising edge of the 1st Clock pulse, the /Q of FF3 will go High, but the Q output of FF0 goes Low, so JK into FF1 is still Low.

After the 2nd Clock pulse, Q of FF0 will go high again. this means the AND gate feeding FF1 has a High from Q of FF0 and /Q of FF3.

So the 3rd clock pulse will toggle FF1 1 to Low.

You can work out the remaining cycles from this Hint.

Look at the attached 4027 image

 

if I change the 10 decoder to 13 decoder
how I can link to FF2 in 13 decoder ?
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..
..
I think the link in 13 decoder go to Q3 & Q2

 

hi,
Sorry, its still not correct.

Consider FF1 input, before the 1st Clock, the JK are both Low. [ because /Q of FF3 is Low]

After the rising edge of the 1st Clock pulse, the /Q of FF3 will go High, but the Q output of FF0 goes Low, so JK into FF1 is still Low.

After the 2nd Clock pulse, Q of FF0 will go high again. this means the AND gate feeding FF1 has a High from Q of FF0 and /Q of FF3.

So the 3rd clock pulse will toggle FF1 1 to Low.

You can work out the remaining cycles from this Hint.

Look at the attached 4027 image

3 days in this question there isn't answer true#

 

3 days in this question there isn't answer true#

hi full,

Are you expecting us to give you the complete answer to this question.??
You have had a number of hints on how to solve it.

E

 

Hello,

Have a look at this page about synchrone counters:
http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol1/cwl3/article1.html

This is one of the links on one of the pages I gave you in my post on the resources thread.

Bertus

 

I think now true

 

Hello,

I have written out the gate expressions in your schematic:

Can you make the timing diagram now?

Bertus

 

I think now true

Several times you have been asked to include the waveforms for the control inputs to the flip flops. That will let us see exactly where you are going wrong so that we can point it out. It's just three signals. But you won't do it. Why not?

It seems like you are just making random changes to your diagram -- and whether you are or not is actually beside the point because, either way, you aren't giving us the information we need to help you effectively.

 

It's time for you to step up and give the answers to the questions asked of you.

If you don't understand the questions...say so. You won't get points taken off....because no one is grading you and really want to help you succeed. You have to help us help you. No one is a mind reader.

On edit ...

The attachment shows the initial conditions according to your problem statement. Can you fill in each and every location for the FF's with the appropriate signal level?