I have a circuit using a CD4017 counter. I'm driving the clock input with a 555 timer generating a 250 msec pulse. I've tied pin5 to pin15, this resets the counter to zero (pin3 hi). BUT, when pin3 goes hi so does pin 10. The next input pulse causes another pair of output pins to go hi and so forth. Sequencing power clears the counter and pin3 is again hi and waiting for an input pulse (I have an R/C circuit on pin15 to reset on power-up).

I'm using a well filtered 12VDC power supply. I have a .1 ufd cap across the P/S input to the chip. I've put .1 ufd and .22 ufd caps across the P/S input pins on all the chips in the circuit. I've tried several unused 4017 chips but the problem continues. I've scoped various points all over the circuit and can find no noise or oscillation.

 

Hi w,
Try it without the R/C power reset components on pin15, I know it may power up incorrectly, but let it step thru its counting sequence. Keep pin 5 to 15 connected.
E

 

Please provide a schematic of the circuitry on the reset pin.

 

Generally the NE555's output was not intended to drive CMOS (though we all do it). I would try adding a 4.7k pullup-resistor to NE555's output so it can switch the fully range and also get there a little more quickly. An LMC555C (CMOS) would work reliably without the pull-up.

Which CD4017 are you using? Some are very fast and you might have to worry about ground bounce and similar effects. Others don't like 12 volts.

I doubt this is related to your problem but will mention it just in case: I'm glad to see that you are bypassing the power supply pins. 0.1 ceramic and 22.0 uf is often used, rather than 0.1 uf and 0.22 uf -not much of a difference between those two.

 

Can you slow down the 555 to 1hz or so then you can see what is happening easier.

Post a picture of the board you have made, chances are there are solder mistakes.

 

Hi w,
Try it without the R/C power reset components on pin15, I know it may power up incorrectly, but let it step thru its counting sequence. Keep pin 5 to 15 connected.
E

Eric,

Thanks for your advice - it was spot on. I removed the R/C reset network on the reset pin (pin 15) and that cleared up the false triggering. I'll probably use the R/C to drive the base of a transistor that will serve as a reset signal, that should provide adequate Isolation between the R/C and the reset pin.

Please explain how you arrived at the idea that the R/C was causing the false triggering.

Thanks again,
Walt

 

Please explain how you arrived at the idea that the R/C was causing the false triggering.

hi Walt,
Adding capacitance into pulsing logic line signals degrades the rising and falling edges of the pulse.
This can cause multiple triggering of a device that is reading the degraded edges.

Many IC devices have Schmitt input circuitry which adds hysteresis to the device, this prevents multiple triggering of the device.
The CD4017 does not have this type of input on its Reset pin.

Please post an image showing how the R/C circuit was connected, so that we can confirm our findings.

E